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Bus Width
8
16
17
18
Avoid MOV P0 instructions for external memory accesses. These instructions
can corrupt input code bytes at port 0.
External signal ALE (address latch enable) facilitates external address latch capture. The address
byte is valid after the ALE pin drives V
to the write (WR#) pin asserting V
data returned from external memory must appear at port 0 before the read (RD#) pin is undriven
(refer to the 8XC251Sx datasheet for exact specifications). Wait states, by definition, affect bus-
timing.
Table 7-2. Instructions for External Data Moves
MOVX @Ri; MOV @Rm; MOV dir8
MOVX @DPTR; MOV @WRj; MOV @WRj+dis; MOV dir16
MOV @DRk; MOV @DRk+dis
MOV @DRk; MOV @DRk+dis
NOTE
. For write cycles, valid data is written to port 0 just prior
OL
. Data remains valid until WR# is undriven. For read cycles,
OL
INPUT/OUTPUT PORTS
Instructions
7-9
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