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State 1
WCLK
ALE
RD#/PSEN#
WAIT#
P0
A0-A7
P2
Figure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State)
State 1
WCLK
ALE
WR#
WAIT#
P0
A0-A7
P2
Figure 13-13. External Data Write (Nonpage Mode, RT Wait State)
EXTERNAL MEMORY INTERFACE
State 2
State 3
RD#/PSEN#
D0-D7
stretched
A8-A15
stretched
State 2
State 3
WR# stretched
D0-D7
A8-A15
State 1 (next cycle)
stretched
A0-A7
A8-A15
A5007-01
State 4
stretched
stretched
A5009-01
13-13
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