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8XC251SA, SB, SP, SQ USER'S MANUAL
Table A-21. Summary of Increment and Decrement Instructions
Increment
INC DPTR
Increment
INC byte
Increment
INC <dest>,<src>
Decrement
DEC byte
Decrement
DEC <dest>,<src>
Mnemonic
<dest>,<src>
A
Rn
dir8
INC;
@Ri
DEC
Rm,#short
WRj,#short
DRk,#short
INC
DPTR
NOTES:
1.
A shaded cell denotes an instruction in the MCS
2.
If this instruction addresses an I/O port (P x , x = 0–3), add 2 to the number of states.
Table A-22. Summary of Multiply, Divide, and Decimal-adjust Instructions
Multiply
Divide
Decimal-adjust ACC
for Addition (BCD)
Mnemonic
<dest>,<src>
AB
MUL
Rmd,Rms
WRjd,WRjs
AB
DIV
Rmd,Rms
WRjd,WRjs
DA
A
NOTES:
1.
A shaded cell denotes an instruction in the MCS
2.
See section A.4, "Instruction Descriptions."
A-16
(DPTR) ← (DPTR) + 1
byte ← byte + 1
dest opnd ← dest opnd + src opnd
byte ← byte – 1
dest opnd ← dest opnd - src opnd
Notes
acc
Reg
Dir byte
Indir RAM
Byte reg by 1, 2, or 4
Word reg by 1, 2, or 4
Double word reg by 1, 2, or 4
Data pointer
®
51 architecture.
MUL <reg1,reg2>
MUL AB
DIV <reg1>,<reg2>
DIV AB
DA A
Notes
Multiply A and B
Multiply byte reg and byte reg
Multiply word reg and word reg
Divide A by B
Divide byte reg by byte reg
Divide word reg by word reg
Decimal adjust acc
®
51 architecture.
Binary Mode
Bytes States Bytes States
1
1
1
1
2
2 (2)
1
3
3
2
3
2
3
4
1
1
(2)
(B:A) = A x B
(2)
(A) = Quotient; (B) =Remainder
(2)
Binary Mode
Bytes States Bytes States
1
5
3
6
3
12
1
10
3
11
3
21
1
1
Source Mode
1
1
2
2
2
2 (2)
2
4
2
1
2
1
2
3
1
1
Source Mode
1
5
2
5
2
11
1
10
2
10
2
20
1
1
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