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8XC251SA, SB, SP, SQ USER'S MANUAL
The PCA WDT generates a reset signal each time a match occurs. To hold off a PCA WDT reset,
the user has three options:
•
periodically change the comparison value in CCAP4H/CCAP4L so a match never occurs
•
periodically change the PCA timer/counter value so a match never occurs
•
disable the module 4 reset output signal by clearing the WDTE bit before a match occurs,
then later re-enable it
The first two options are more reliable because the WDT is not disabled as in the third option.
The second option is not recommended if other PCA modules are in use, since the five modules
share a common time base. Thus, in most applications the first option is the best one.
PCA Timer/Counter
Count
Input
CH
(8 Bits)
(8 Bits)
"0"
Reset
Write to
CCAP4L
"1"
Write to CCAP4H
9-10
Compare/Capture
Module
CL
CCAP4H
CCAP4L
(8 Bits)
(8 Bits)
16-Bit
Comparator
Enable
X
ECOM4
0
7
Figure 9-4. PCA Watchdog Timer Mode
Match
WDTE
CMOD.6
0
1
CCAPM4 Mode Register
X = Don't Care
PCA WDT Reset
X
0
X
0
A4165-01
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