Intel Cyclone V GT FPGA Development Kit User Manual
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Intel Cyclone V GT FPGA Development Kit User Manual

Intel Cyclone V GT FPGA Development Kit User Manual

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Cyclone
V GT FPGA Development
Kit User Guide
792833
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2024.02.21

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Summary of Contents for Intel Cyclone V GT FPGA Development Kit

  • Page 1 ® Cyclone V GT FPGA Development Kit User Guide 792833 Online Version Send Feedback 2024.02.21...

  • Page 2: Table Of Contents

    6.4.2. Power Monitor Controls................38 6.5. The Clock Control....................38 6.5.1. Clock Control Features................39 6.5.2. Clock Control Controls................39 7. Document Revision History for Cyclone V GT FPGA Development Kit User Guide...41 ® Cyclone V GT FPGA Development Kit User Guide...
  • Page 3 Contents A. Programming the Flash Memory Device................ 42 A.1. CFI Flash Memory Map..................42 A.2. Preparing Design Files for Flash Programming............43 A.3. Creating Flash Files Using the Nios II EDS............... 43 A.4. Converting Additional Files..................44 A.5. Programming Flash Memory Using the Nios II EDS........... 44 A.6.

  • Page 4: Kit Features

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 5: Cyclone V Gt Fpga Development Kit Installer

    — Program a device and verify your design in hardware. The Intel FPGA IP Evaluation Mode hardware evaluation feature is an evaluation tool for prototyping only. You must purchase a license to use an Intel FPGA IP function in production.

  • Page 6: Getting Started

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 7: References For Getting Started

    2. Getting Started 792833 | 2024.02.21 2.3. References for Getting Started Use the following links to check the Intel website for other related information: • For complete information about the FPGA development board hardware, refer to the Cyclone V GT FPGA Development Board Reference Manual.

  • Page 8: Software Installation

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 9: Installing The Development Kit

    3.3. Installing the Development Kit Following are the steps to install the development kit: 1. Download the Cyclone V GT FPGA Development Kit installer from the Cyclone V GT FPGA Development Kit page of the Intel website. Alternatively, you can request a development kit DVD from the Intel Kit Installations DVD Request Form page of the Intel website.

  • Page 10: Installing The Intel Fpga Download Cable Ii Driver

    Contains demonstration applications. demos Contains the kit documentation. documents Contains the sample design files for the Cyclone V GT FPGA Development Kit. examples Contains the original data programmed onto the board before shipment. Use this data to restore factory_recovery the board with its original factory contents.

  • Page 11: Development Board Setup

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 12: Factory Default Switch And Jumper Settings

    4. Development Board Setup 792833 | 2024.02.21 Related Information Factory Default Switch and Jumper Settings on page 12 4.2. Factory Default Switch and Jumper Settings The following figure shows the default switch settings for the top side of the Cyclone V GT FPGA development board.
  • Page 13 4. Development Board Setup 792833 | 2024.02.21 Figure 3. Default Switch Settings on the Board Bottom (Not installed = 2.5V) C5_VCCIO_VAR 1.2V 1.5V 1.8V 1 2 3 4 Note: The following tables do not describe user DIP switches. To restore the switches to the default settings, perform the following: 1.
  • Page 14 4. Development Board Setup 792833 | 2024.02.21 Table 4. SW4 DIP Switch Settings Switch Board Label Function Default Position CLKSEL Switch 1 has the following options: • ON (logical 0) = SMA input clock select. • OFF (logical 1) = Programmable oscillator clock select. CLKEN —...

  • Page 15: Configuring The Max V Device To Program Epcq

    4.3. Configuring the MAX V Device to Program EPCQ It is possible to configure the FPGA from the EPCQ device. However, the MAX V design provided with the Cyclone V GT FPGA development kit does not allow you to store a design in the EPCQ configuration device.

  • Page 16: Restoring The Flash Device To The Factory Settings

    1. Set the board switches to the factory default settings described inFactory Default Switch and Jumper Settings. 2. Start the Intel Quartus Prime Programmer to configure the FPGA with a .sof capable of flash programming.For more information, refer to Configuring the FPGA Using the Intel Quartus Prime Programmer.

  • Page 17: Configuring The Fpga Using The Intel Quartus Prime Programmer

    4. Development Board Setup 792833 | 2024.02.21 To ensure that you have the most up-to-date factory restore files and information about this product, refer to the Cyclone V GT FPGA Development Kit page of the Intel website. Related Information •...

  • Page 18: Board Update Portal

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 19: Using The Board Update Portal To Write User Designs

    5. Board Update Portal 792833 | 2024.02.21 You can also navigate directly to the Cyclone V GT FPGA Development Kit page of the Intel website to determine if you have the latest kit software. Related Information Cyclone V GT FPGA Development Kit 5.2.

  • Page 20: Board Test System

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 21: Preparing To Run The Board Test System

    The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the Signal Tap II Embedded Logic Analyzer. As the Intel Quartus Prime programmer uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time out.

  • Page 22: The System Info Tab

    The design begins running in the FPGA. The corresponding GUI application tabs that interface with the design are now enabled. If the Board Test System application is open while you configure FPGAs with the Intel Quartus Prime Programmer, you may need to restart the Board Test System.
  • Page 23 6. Board Test System 792833 | 2024.02.21 Figure 6. The System Info Tab The following sections describe the controls on the System Info tab. ® Cyclone V GT FPGA Development Kit User Guide Send Feedback...
  • Page 24 6. Board Test System 792833 | 2024.02.21 6.3.2.1. Power Tree Figure 7. Power Tree Diagram (DK-DEV-5CGTD9N-B) 19V 6.32A(max) 3.3V_MUX LTC3855EUJ DC Input (J8) (U40) 12V_MUX 3.3V_OUT LTC4352 3.3V_MUX (D31, D33) 3.3V_PCIE 3.3V 12V_OUT LTC4357 12V_MUX (U44, U45) 12V_PCIE Voltage Current 1.1V_REG_VCC Telemetry LTC3613EWKH...
  • Page 25 <install dir>\kits directory. \cycloneVGT_5cgtfd9ef35_fpga\examples Newer revisions of this code might be available on the Cyclone V GT FPGA Development Kit page of the Intel website. • MAC—Indicates the MAC address of the board. Related Information Cyclone V GT FPGA Development Kit 6.3.2.4.

  • Page 26: The Gpio Tab

    13 table for detailed settings. For details on the JTAG chain, refer to the Cyclone V GT FPGA Development Board Reference Manual. For Intel FPGA Download Cable II configuration details, refer to the On-Board Intel FPGA Download Cable II User Guide page.
  • Page 27 6. Board Test System 792833 | 2024.02.21 Figure 8. The GPIO Tab Note: The picture of the development kit is only a reference and might be different from the latest one. The following sections describe the controls on the GPIO tab. 6.3.3.1.

  • Page 28: The Flash Tab

    6. Board Test System 792833 | 2024.02.21 6.3.3.4. Push Buttons This control displays the current state of the board user push buttons. Press a push button on the board to see the graphical display change accordingly. 6.3.4. The Flash Tab The Flash tab allows you to read and write flash memory on your board.

  • Page 29: The Ddr3X40 And Ddr3X64 Tabs

    6. Board Test System 792833 | 2024.02.21 6.3.4.3. Write Writes the flash memory on your board. To update the flash memory contents: • Type in values in the memory table cells. • Press Enter, and click Write. The application writes the new values to flash memory and then reads the values back to guarantee that the memory table accurately reflects the memory contents.
  • Page 30 6. Board Test System 792833 | 2024.02.21 Figure 10. The DDR3x40 Tab The following figure shows the DDR3x64 tab. Except for the tab name and photograph, this tab is identical to the DDR3x40 tab. ® Cyclone V GT FPGA Development Kit User Guide Send Feedback...
  • Page 31 6. Board Test System 792833 | 2024.02.21 Figure 11. The DDR3x64 Tab The following sections describe the controls on the DDR3x40 and DDR3x64 tabs. 6.3.5.1. Start Initiates DDR3 memory transaction performance analysis. 6.3.5.2. Stop Terminates the transaction performance analysis. 6.3.5.3. Performance Indicators Display current transaction performance analysis information collected since you last clicked Start: •...

  • Page 32: The Hsma Tab

    6. Board Test System 792833 | 2024.02.21 6.3.5.4. Error Control This group displays data errors detected during analysis and allows you to insert errors: • Detected Errors—Displays the number of data errors detected in the hardware. • Inserted Errors—Displays the number of errors inserted into the transaction stream.
  • Page 33 6. Board Test System 792833 | 2024.02.21 You must have the loopback HSMA installed on the HSMC Port A connector for this test to work correctly. The following sections describe the controls on the HSMA tab. 6.3.6.1. Start, Stop The Start and Stop controls at the bottom-right of this tab allow you to start and stop testing for all three ports.

  • Page 34: The Hsmb Tab

    6. Board Test System 792833 | 2024.02.21 • Pre—Not available. — First post—Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer. Second post—Not available. • Equalizer—Specifies the setting for the receiver equalizer. • DC gain—Specifies the DC portion of the receiver equalizer. Data Type—Specifies the type of data contained in the transactions.
  • Page 35 6. Board Test System 792833 | 2024.02.21 Figure 13. The HSMB Tab You must have the loopback HSMB installed on the HSMC Port B connector for this test to work correctly. The following sections describe the controls on the HSMB tab. 6.3.7.1.
  • Page 36 6. Board Test System 792833 | 2024.02.21 BER—Displays the bit error rate of the interface. Status • PLL lock—Displays Yes if the PLL is locked. • Pattern Sync—Displays Yes if the receiver has detected the input data pattern. Start—Starts the PRBS data test and begins to monitor and update screen with live test results.

  • Page 37: The Power Monitor

    6. Board Test System 792833 | 2024.02.21 6.4. The Power Monitor You can start the Power Monitor application with the following: • The Power Monitor button on the Board Test System GUI. • The PowerMonitor.exe application that resides in the <install dir>\kits directory.

  • Page 38: Power Monitor Controls

    \cycloneVGT_5cgtfd9ef35_fpga\examples\max5 Newer revisions of this code might be available on the Cyclone V GT FPGA Development Kit page of the Intel website. • Power rail—Indicates the currently-selected power rail. After selecting the desired rail, click Reset to refresh the screen with updated board readings.

  • Page 39: Clock Control Features

    6. Board Test System 792833 | 2024.02.21 6.5.1. Clock Control Features The Clock Control application sets the Si570 and Si571 programmable oscillators to any frequency between 10 MHz and 810 MHz. • The Si570 (not the Si571) oscillator drives a 1-to-6 buffer that drives a copy of the clock to the following areas of the FPGA: —...
  • Page 40 Target frequency control for the Si570 and Si571 oscillators. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Intel recommends resetting the FPGA logic after changing frequencies.

  • Page 41: Document Revision History For Cyclone V Gt Fpga Development Kit User Guide

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 42: Programming The Flash Memory Device

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 43: Preparing Design Files For Flash Programming

    792833 | 2024.02.21 Intel recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Intel tools. If you unintentionally overwrite the factory hardware or factory software image, refer to Restoring the Flash Device to the Factory Settings.

  • Page 44: Converting Additional Files

    LCD or if the Config Done LED (D7) does not illuminate, continue to step 4 to load the FPGA with a flash-writing design. 4. Run the Intel Quartus Prime Programmer to configure the FPGA with a .sof capable of flash programming. Refer to Restoring the MAX V CPLD to the Factory Settings for more information.

  • Page 45: Programming Flash Memory Using The Board Update Portal

    A. Programming the Flash Memory Device 792833 | 2024.02.21 10. After programming completes, if you have a software file to program, type the following Nios II EDS command: nios2-flash-programmer --base=0x00000000 <yourfile>_sw.flash 11. Set the SW4.3 DIP switch to the FACT OFF (logic 1) position and power cycle the board.

  • Page 46: Additional Information

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 47: Safety Warnings

    B. Additional Information 792833 | 2024.02.21 B.1.1. Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system.

  • Page 48: Safety Cautions

    B. Additional Information 792833 | 2024.02.21 Power Cord Requirements The plug on the power cord must be a grounding-type male plug designed for use in your region. It must have certification marks showing certification by an agency in your region. The connector that plugs into the appliance inlet of the power supply must be an IEC 320, sheet C13, female connector.
  • Page 49 B. Additional Information 792833 | 2024.02.21 Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan. Electro-Magnetic Interference (EMI) This equipment has not been tested for compliance with emission limits of FCC and similar international regulations.
  • Page 50 Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

  • Page 51: Compliance Information

    B. Additional Information 792833 | 2024.02.21 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste. B.2. Compliance Information...

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