Table of Contents
Advertisement
CMOD
7
CIDL
WDTE
Bit
Bit
Number
Mnemonic
7
CIDL
6
WDTE
5:3
—
2:1
CPS1:0
0
ECF
Figure 9-7. CMOD: PCA Timer/Counter Mode Register
—
—
PCA Timer/Counter Idle Control:
CIDL = 1 disables the PCA timer/counter during idle mode. CIDL = 0
allows the PCA timer/counter to run during idle mode.
Watchdog Timer Enable:
WDTE = 1 enables the watchdog timer output on PCA module 4.
WDTE = 0 disables the PCA watchdog timer output.
Reserved:
The values read from these bits are indeterminate. Write zeros to these
bits.
PCA Timer/Counter Input Select:
CPS1 CPS0
0
0
F
/12
OSC
0
1
F
/4
OSC
1
0
Timer 0 overflow
1
1
External clock at ECI pin (maximum rate = F
PCA Timer/Counter Interrupt Enable:
ECF = 1 enables the CF bit in the CCON register to generate an interrupt
request.
PROGRAMMABLE COUNTER ARRAY
Address:
Reset State:
—
CPS1
CPS0
Function
S:D9H
00XX X000B
0
ECF
/8 )
OSC
9-13
Advertisement
Table of Contents
