Table of Contents
Advertisement
P1.7/CEX/
RD1:0
A17/WCLK
0 0
A17
0 1
P1.7/CEX4/
WCLK
1 0
P1.7/CEX4/
WCLK
1 1
P1.7/CEX4/
WCLK
NOTE: RD1:0 are bits 3:2 of configuration byte UCONFIG0 (See Figure 4-3 on page 4-6).
Table B-3. Memory Signal Selections (RD1:0)
P3.7/RD#/A16/
PSEN#
A16
Asserted for
all addresses
A16
Asserted for
all addresses
P3.7 only
Asserted for
all addresses
RD# asserted
Asserted for
≥ 80:0000H
for addresses
≤ 7F:FFFFH
SIGNAL DESCRIPTIONS
WR#
Asserted for writes to
256-Kbyte external
all memory locations
memory
Asserted for writes to
128-Kbyte external
all memory locations
memory
Asserted for writes to
64-Kbyte external
all memory locations
memory. One
additional port pin.
Asserted only for
64-Kbyte external
®
writes to MCS
51
memory. Compatible
microcontroller data
with MCS 51 micro-
memory locations.
controllers.
Features
B-7
Advertisement
Table of Contents
