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Table 5-4. Addressing Modes for Data Instructions in the MCS
Address Range of
Mode
Operand
00:0000H
Register
(R0–R7, WR0–WR3,
DR0, DR2) (1)
Immediate,
N.A. (Operand is in the
2 bits
instruction)
Immediate,
N.A. (Operand is in the
8 bits
instruction)
Immediate,
N.A. (Operand is in the
16 bits
instruction)
00:0000H–00:007FH
Direct,
8 address bits
SFRs
Direct,
00:0000H–00:FFFFH
16 address bits
Indirect,
00:0000H–00:FFFFH
16 address bits
Indirect,
00:0000H–FF:FFFFH
24 address bits
Displacement,
00:0000H–00:FFFFH
16 address bits
Displacement,
00:0000H
24 address bits
NOTES:
1.
These registers are accessible in the memory space as well as in the register file (see section 3.3,
"8XC251SA, SB, SP, SQ Register File."
2.
The MCS 251 architecture supports SFRs in locations S:000H–S:1FFH; however, in the 8XC251S x ,
all SFRs are in the range S:080H–S:0FFH.
Assembly Language
–
00:001FH
–
R0
R15, WR0
–
DR0
DR28, DR56, DR60
#short = 1, 2, or 4
#data8 = #00H–#FFH
#data16 = #0000H
dir8 = 00:0000H–00:007FH
dir8 = S:080H
or SFR mnemonic
dir16 = 00:0000H–00:FFFFH
@WR0–@WR30
@DR0–@DR30, @DR56,
@DR60
@WRj + dis16 =
@WR0 + 0H through
@WR30 + FFFFH
@DRk + dis24 =
@DR0 + 0H through
–
FF:FFFFH
@DR28 + FFFFH,
@DR56 + (0H–FFFFH),
@DR60 + (0H–FFFFH)
®
Notation
–
R0
–
WR30,
DR2 are in the register bank
currently selected by the
PSW and PSW1.
Used only in increment and
decrement instructions.
–
#FFFFH
On-chip RAM
–
S:1FFH (2)
SFR address
Upper 8 bits of DRk must be
00H.
Offset is signed; address
wraps around in region 00:.
Offset is signed, upper 8 bits
of DRk must be 00H.
PROGRAMMING
251 Architecture
Comments
R7, WR0–WR6, DR0, and
5-7
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