Intel 8XC251SA User Manual page 175

The serial port control (SCON) register (Figure 10-2) configures and controls the serial port.
SCON
7
FE/SM0 SM1
Bit Bit
Number Mnemonic
7 FE
SM0
6 SM1
5 SM2
4 REN
3 TB8
2 RB8
Figure 10-2. SCON: Serial Port Control Register
SM2 REN
Framing Error Bit:
To select this function, set the SMOD0 bit in the PCON register. Set by
hardware to indicate an invalid stop bit. Cleared by software, not by valid
frames.
Serial Port Mode Bit 0:
To select this function, clear the SMOD0 bit in the PCON register.
Software writes to bits SM0 and SM1 to select the serial port operating
mode. Refer to the SM1 bit for the mode selections.
Serial Port Mode Bit 1:
Software writes to bits SM1 and SM0 (above) to select the serial port
operating mode.
SM0 SM1 Mode Description
0 0 0 Shift register
0 1 1 8-bit UART
1 0 2 9-bit UART
1 1 3 9-bit UART
†
Select by programming the SMOD bit in the PCON register (see section
10.6, "Baud Rates").
Serial Port Mode Bit 2:
Software writes to bit SM2 to enable and disable the multiprocessor
communication and automatic address recognition features. This allows
the serial port to differentiate between data and command frames and to
recognize slave and broadcast addresses.
Receiver Enable Bit:
To enable reception, set this bit. To enable transmission, clear this bit.
Transmit Bit 8:
In modes 2 and 3, software writes the ninth data bit to be transmitted to
TB8. Not used in modes 0 and 1.
Receiver Bit 8:
Mode 0: Not used.
Mode 1 (SM2 clear): Set or cleared by hardware to reflect the stop bit
received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth
data bit received.
Address:
Reset State:
TB8 RB8
Function
Baud Rate
F /12
OSC
Variable
†
F /32 or F
OSC
Variable
SERIAL I/O PORT
98H
0000 0000B
0
TI RI
†
/64
OSC
10-3