Intel 8XC251SA User Manual page 405

Table C-2. Core SFRs
Mnemonic Name
†
ACC Accumulator
†
B B Register
PSW Program Status Word
PSW1 Program Status Word 1
†
SP Stack Pointer – LSB of SPX
†
SPH Stack Pointer High – MSB of SPX
†
DPTR Data Pointer (2 bytes)
†
DPL Low Byte of DPTR
†
DPH High Byte of DPTR
†
DPXL Data Pointer, Extended Low
PCON Power Control
IE0 Interrupt Enable Control 0
IPH0 Interrupt Priority Control High 0
IPL0 Interrupt Priority Control Low 0
WCON Wait State Control Register
†
These SFRs can also be accessed by their corresponding registers in the
register file (see Table 3-4 on page 3-15 and Table C-7).
Table C-3. I/O Port SFRs
Mnemonic
P0
P1
P2
P3
Name Address
Port 0 S:80H
Port 1 S:90H
Port 2 S:A0H
Port 3 S:B0H
REGISTERS
Address
S:E0H
S:F0H
S:D0H
S:D1H
S:81H
S:BEH
—
S:82H
S:83H
S:84H
S:87H
S:A8H
S:B7H
S:B8H
S:A7H
C-3