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8XC251SA, SB, SP, SQ USER'S MANUAL
Read
Latch
Internal
Bus
Write to
Latch
Read
Pin
When port 0 and port 2 are used for an external memory cycle, an internal control signal switches
the output-driver input from the latch output to the internal address/data line. Section 7.8, "Exter-
nal Memory Access," discusses the operation of port 0 and port 2 as the external address/data bus.
Port 0 and port 2 are precluded from use as general purpose I/O ports when
used as address/data bus drivers.
Port 0 internal pullups assist the logic-one output for memory bus cycles only.
Except for these bus cycles, the pullup FET is off. All other port 0 outputs are
open drain.
7-4
Address
D
Q
P2. x
Latch
CL
Q#
Figure 7-3. Port 2 Structure
NOTE
Control
1
0
V
CC
Internal
Pullup
P2. x
A2240-01
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