Priority Queue Status Register (Pqsr) Field Descriptions - Texas Instruments TMS320C6000 DSP Reference Manual

EDMA Control Registers
3.5.2 Priority Queue Status Register (PQSR)
Figure 3−5. Priority Queue Status Register (PQSR)
31
Legend: R = Read only; -n = value after reset
Table 3−11. Priority Queue Status Register (PQSR) Field Descriptions
Bit Field symval
31−3 Reserved −
2−0 PQ OF(value)
DEFAULT
†
For CSL implementation, use the notation EDMA_PQSR_PQ_symval.
3-14 TMS320C621x/C671x EDMA
The priority queue status register (PQSR) indicates whether the transfer
controller is empty on each priority level. The PQSR is shown in Figure 3−5
and described in Table 3−11. The priority queue status (PQ) bit provides the
status of the queues as well as any active transfers. When the PQ bits are set
to 111b, there are no requests pending in the respective priority level queues
and no transfer is in progress. For example, if bit 0 (PQ0) is set to 1, all L2
requests for data movement have been completed and there are no requests
pending in the priority level 0 queue.
The PQ bits are mainly used for emulation or debugging and typically should
not be used by an application.
Reserved
R-0
†
Value Description
0 Reserved. You should always write 0 to this field.
0−7h Priority queue status. A 1 in the PQ bit indicates that there are no
requests pending in the respective priority level queue.
7h There are no requests pending in the priority level queues.
3 2 1 0
PQ2 PQ1 PQ0
R-1 R-1 R-1
SPRU234B