Floating-Point Status Register (Stf); Floating-Point Unit Status Register (Stf); Floating-Point Unit Status (Stf) Register Field Descriptions - Texas Instruments TMS320C28 series Reference Manual

CPU Registers

2.1.1 Floating-Point Status Register (STF)

The floating-point status register (STF) reflects the results of floating-point operations. There are three
basic rules for floating point operation flags:
1. Zero and negative flags are set based on moves to registers.
2. Zero and negative flags are set based on the result of compare, minimum, maximum, negative and
absolute value operations.
3. Overflow and underflow flags are set by math instructions such as multiply, add, subtract and 1/x.
These flags may also be connected to the peripheral interrupt expansion (PIE) block on your device.
This can be useful for debugging underflow and overflow conditions within an application.
As on the C28x, program flow is controlled by C28x instructions that read status flags in the status register
0 (ST0) . If a decision needs to be made based on a floating-point operation, the information in the STF
register needs to be loaded into ST0 flags (Z,N,OV,TC,C) so that the appropriate branch conditional
instruction can be executed. The
STF flags into the respective bits of ST0. When this instruction executes, it will also clear the latched
overflow and underflow flags if those flags are specified.
Example 2-1. Moving STF Flags to the ST0 Register
Loop:
MOV32 R0H,*XAR4++
MOV32 R1H,*XAR3++
CMPF32 R1H, R0H
MOVST0 ZF, NF
BF Loop, GT
31 30
SHDWS
R/W-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-2. Floating-point Unit Status (STF) Register Field Descriptions
Bits Field Value
31 SHDWS
0
1
30 - 10 Reserved 0
9 RND32
0
1
8 - 7 Reserved 0
16 CPU Register Set
MOVST0 FLAG
; Move ZF and NF to ST0
; Loop if (R1H > R0H)
Figure 2-2. Floating-point Unit Status Register (STF)
10 9 8
RND32 Reserved
R/W-0
Shadow Mode Status Bit
This bit is forced to 0 by the RESTORE instruction.
This bit is set to 1 by the SAVE instruction.
This bit is not affected by loading the status register either from memory or from the shadow values.
Reserved for future use
Round 32-bit Floating-Point Mode
If this bit is zero, the MPYF32, ADDF32 and SUBF32 instructions will round to zero (truncate).
If this bit is one, the MPYF32, ADDF32 and SUBF32 instructions will round to the nearest even value.
Reserved for future use
instruction is used to load the current value of specified
Reserved
R-0
7 6 5
TF ZI
R-0 R/W-0 R/W-0 R/W-0
Description
SPRUEO2A – June 2007 – Revised August 2008
www.ti.com
4 3 2 1
NI ZF NF LUF
R/W-0 R/W-0 R/W-0
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16
0
LVF
R/W-0