Pll Control/Status Register (Pllcsr); Pll Control/Status Register (Pllcsr) Field Descriptions - Texas Instruments TMS320C6000 DSP Reference Manual

Registers
4.2

PLL Control/Status Register (PLLCSR)

The PLL control/status register (PLLCSR) is shown in Figure 4 and described
in Table 3.
Figure 4.

PLL Control/Status Register (PLLCSR)

31
15
Reserved
R-0
Legend: R = Read only; R/W = Read/write; -n = value after reset
Table 3.

PLL Control/Status Register (PLLCSR) Field Descriptions

†
Bit field symval
31–7 Reserved –
6 STABLE OF(value)
5–4 Reserved –
3 PLLRST
0
1
2 Reserved –
† For CSL implementation, use the notation PLL_PLLCSR_field_symval
16 Phase-Locked Loop (PLL) Controller
Reserved
R-0
7 6 5
STABLE Reserved
R-1 R/W-0
†
Value Description
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
Oscillator input stable bit indicates if the OSCIN/CLKIN input
has stabilized. The STABLE bit is set to 1 after the reset
controller counts 4096 input clock cycles after the RESET
signal is asserted high.
0 OSCIN/CLKIN input is not yet stable. Oscillator counter is not
finished counting.
1 OSCIN/CLKIN input is stable.
0 Reserved. The reserved bit location is always read as 0.
Always write a 0 to this location.
PLL reset bit.
0 PLL reset is released.
1 PLL reset is asserted.
0 Reserved. The reserved bit location is always read as 0.
Always write a 0 to this location.
4 3 2
PLLRST — PLLPWRDN
R/W-1 R/W-0 R/W-0
16
1 0
PLLEN
R/W-0
SPRU233A