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Registers
4.2
Primary IDE Channel DMA Status Register (BMISP)
The primary IDE channel DMA status register (BMISP) is a 16-bit wide register used to indicate interrupt
presence, DMA error condition, as well as DMA activity (state). BMISP is shown in
in
Table
13.
15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 13. Primary IDE Channel DMA Status Register (BMISP) Field Descriptions
Bit
Field
Value
15-4
Reserved
0
3
IORDYINT
0
1
2
INTRSTAT
0
1
1
DMAERROR
0
1
0
IDEACT
0
1
36
ATA Controller
Figure 4. Primary IDE Channel DMA Status Register (BMISP)
4
R-0
Description
Reserved
IORDY timeout. Write a 1 to clear this bit.
IORDY timer functionality is disabled.
IORDY timer functionality is enabled and the WAIT (IORDY) timer times-out before the target device
being accessed deasserts ATA_IORDY during a transfer.
IDE interrupt status. INTRSTAT is set by the rising edge of the IDE device interrupt pin; write a 1 to
clear this bit. After a DMA transfer is initiated, INTRSTAT is set when all data has been transferred to
system memory (read commands) or to the device (write commands). If a DMA transfer has not been
initiated, software can use INTRSTAT to determine if an IDE device has asserted its interrupt line.
Because INTRSTAT is set at the rising edge of the IDE interrupt, INTRSTAT will not necessarily
represent the current state of the IDE interrupt signal.
IDE interrupt is inactive.
IDE interrupt is active.
DMA error. DMAERROR is set when the controller encounters an error in transferring data to or from
memory; write a 1 to clear this bit.
DMAERROR can only be set due to an internal buffer overflow or underflow. Under normal conditions,
this should not occur.
No DMA error.
DMA buffer underflow or overflow.
IDE active. IDEACT is set when the DMASTART bit in BMICP is written with a 1. IDEACT is cleared
when the final DMA transfer for a region is performed (that is, where the EOT bit is set in the region
descriptor) and all data has been transferred to system memory (device read) or to the device (device
write), or when a DMA transfer is aborted by writing the DMASTART bit with a 0. See
IDE is inactive
IDE is active.
Reserved
R-0
3
2
IORDYINT
INTRSTAT
R/W1C-0
R/W1C-0
www.ti.com
Figure 4
and described
8
1
0
DMAERROR
IDEACT
R/W1C-0
R-0
Table
6.
SPRUEQ3 – December 2007
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