Error And Status Register (Canes); Error And Status Register (Canes) Field Descriptions - Texas Instruments TMS320x281 series Reference Manual

Error and Status Register (CANES)

2.13 Error and Status Register (CANES)

The status of the CAN module is shown by the Error and Status Register (CANES) and the error counter
registers, which are described in this section.
The error and status register comprises information about the actual status of the CAN module and
displays bus error flags as well as error status flags. If one of these error flags is set, then the current
state of all other error flags is frozen. i.e. Only the first error is stored. In order to update the CANES
register subsequently, the error flag which is set has to be acknowledged by writing a 1 to it. This action
also clears the flag bit.
31
Reserved
R-0
15
LEGEND: R = Read; C = Clear; -n = value after reset
Bit Field
31:25 Reserved
24 FE
23 BE
22 SA1
21 CRCE
20 SE
19 ACKE
18 BO
42 eCAN Registers
Figure 2-13. Error and Status Register (CANES)
25
Reserved
R-0
Table 2-13. Error and Status Register (CANES) Field Descriptions
Value Description
Reads are undefined and writes have no effect.
Form error flag
1 A form error occurred on the bus. This means that one or more of the fixed-form bit fields had the
wrong level on the bus.
0 No form error detected; the CAN module was able to send and receive correctly.
Bit error flag
1 The received bit does not match the transmitted bit outside of the arbitration field or during
transmission of the arbitration field, a dominant bit was sent but a recessive bit was received.
0 No bit error detected.
Stuck at dominant error. The SA1 bit is always at 1 after a hardware reset, a software reset, or a
Bus-Off condition. This bit is cleared when a recessive bit is detected on the bus.
1 The CAN module never detected a recessive bit.
0 The CAN module detected a recessive bit.
CRC error.
1 The CAN module received a wrong CRC.
0 The CAN module never received a wrong CRC.
Stuff error.
1 A stuff bit error occurred.
0 No stuff bit error occurred.
Acknowledge error.
1 The CAN module received no acknowledge.
0 All messages have been correctly acknowledged.
Bus-off status. The CAN module is in bus-off state.
1 There is an abnormal rate of errors on the CAN bus. This condition occurs when the transmit error
counter (CANTEC) has reached the limit of 256. During Bus Off, no messages can be received or
transmitted. The bus-off state can be exited by clearing the CCR bit in CANMC register or if the
Auto Bus On (ABO) (CANMC.7) bit is set, after 128 * 11 receive bits have been received. After
leaving Bus Off, the error counters are cleared.
0 Normal operation
24 23 22 21
FE BE SA1 CRCE
RC-0 RC-0 R-1 RC-0
6 5
SMA
R-0
SPRU074F – May 2002 – Revised January 2009
www.ti.com
20 19 18 17
SE ACKE BO EP
RC-0 RC-0 RC-0 RC-0
4 3 2 1
CCE PDA Rsvd RM
R-1 R-0 R-0 R-0
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16
EW
RC-0
0
TM
R-0