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15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Bit
Field
15-9
Reserved
8
3VSTAT
7-4
Reserved
3
ACTIVEWAITS
2
STDBYWAITS
1-0
PWRS
(1)
This register is EALLOW protected. See
(2)
This register is protected by the Code Security Module (CSM). See
SPRUFB0C – September 2007 – Revised May 2009
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Figure 1-6. Flash Status Register (FSTATUS)
Reserved
R-0
4
R-0
Table 1-4. Flash Status Register (FSTATUS) Field Descriptions
Value
Reserved
Flash Voltage (V
DD3VFL
the pump module went to a high level. This signal indicates that the flash 3.3-V supply went out of
the allowable range.
0
Writes of 0 are ignored.
1
When this bit reads 1, it indicates that the flash 3.3-V supply went out of the allowable range.
Clear this bit by writing a 1.
Reserved
Bank and Pump Standby To Active Wait Counter Status Bit. This bit indicates whether the
respective wait counter is timing out an access.
0
The counter is not counting.
1
The counter is counting.
Bank and Pump Sleep To Standby Wait Counter Status Bit. This bit indicates whether the
respective wait counter is timing out an access.
0
The counter is not counting.
1
The counter is counting.
Power Modes Status Bits. These bits indicate which power mode the flash/OTP is currently in.
The PWRS bits are set to the new power mode only after the appropriate timing delays have
expired.
00
Pump and bank in sleep mode (lowest power)
01
Pump and bank in standby mode
10
Reserved
11
Pump and bank active and in read mode (highest power)
Section 5.2
for more information.
3
ACTIVEWAITS
STDBYWAITS
R-0
Description
) Status Latch Bit. When set, this bit indicates that the 3VSTAT signal from
Chapter 2
for more information.
Flash and OTP Registers
9
2
1
PWRS
R-0
R-0
(1) (2)
Flash and OTP Memory Blocks
8
3VSTAT
R/W1C-0
0
23
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