Edma Channel Interrupt Pending Register (Cipr) Field Descriptions - Texas Instruments TMS320C6000 DSP Reference Manual

3.5.3 EDMA Channel Interrupt Pending Register (CIPR)
Figure 3−6. EDMA Channel Interrupt Pending Register (CIPR)
31
15 14
CIP15 CIP14
R/W-0 R/W-0
7 6
CIP7 CIP6
R/W-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 3−12. EDMA Channel Interrupt Pending Register (CIPR) Field Descriptions
Bit Field symval
31−16 Reserved −
15−0 CIP OF(value)
DEFAULT
−
†
For CSL implementation, use the notation EDMA_CIPR_CIP_symval.
SPRU234B
The EDMA channel interrupt pending register (CIPR) is shown in Figure 3−6
and described in Table 3−12.
Reserved
13 12
CIP13 CIP12
R/W-0 R/W-0
5 4
CIP5 CIP4
R/W-0 R/W-0
† Value Description
0 Reserved. You should always write 0 to this field.
0−FFFFh Channel interrupt pending. When the TCINT bit in the channel
options parameter (OPT) is set to 1 for an EDMA channel and
a specific transfer complete code (TCC) is provided by the
EDMA transfer controller, the EDMA channel controller sets a
bit in the CIP field.
0 EDMA channel interrupt is not pending.
1 EDMA channel interrupt is pending.
R-0
11 10
CIP11 CIP10
R/W-0 R/W-0
3 2
CIP3 CIP2
R/W-0 R/W-0
TMS320C621x/C671x EDMA
EDMA Control Registers
16
9 8
CIP9 CIP8
R/W-0 R/W-0
1 0
CIP1 CIP0
R/W-0 R/W-0
3-15