Agilent Technologies 16718A Help Volume page 121

Logic analyzer
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Chapter 3: Reference
The Format Tab
clock bits span more than one pod pair.
See Also
"Formatting Labels for Logic Analyzer Probes" on page 53
"To manually adjust sampling positions" on page 46
"To automatically adjust sampling positions" on page 43
"Importing Netlist and ASCII Files" on page 121
120
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