Texas Instruments TMS320VC5402 Datasheet

Fixed-point digital signal processor

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Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

17- 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Data Bus With a Bus-Holder Feature

Extended Addressing Mode for 1M

Maximum Addressable External Program

Space

4K x 16-Bit On-Chip ROM

16K x 16-Bit Dual-Access On-Chip RAM

Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

Block-Memory-Move Instructions for

Efficient Program and Data Management

Instructions With a 32-Bit Long Word

Operand

Instructions With Two- or Three-Operand

Reads

NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview

(literature number SPRU307).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

FIXED POINT DIGITAL SIGNAL PROCESSOR

16-Bit

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251–1443

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

Arithmetic Instructions With Parallel Store

and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank

Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

– Two Multichannel Buffered Serial Ports

(McBSPs)

– Enhanced 8-Bit Parallel Host-Port

Interface (HPI8)

– Two 16-Bit Timers

– Six-Channel Direct Memory Access

(DMA) Controller

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

†

IEEE Std 1149.1

(JTAG) Boundary Scan

Logic

10-ns Single-Cycle Fixed-Point Instruction

Execution Time (100 MIPS) for 3.3-V Power

Supply (1.8-V Core)

Available in a 144-Pin Plastic Low-Profile

Quad Flatpack (LQFP) (PGE Suffix) and a

144-Pin Ball Grid Array (BGA) (GGU Suffix)

2000, Texas Instruments Incorporated

TMS320VC5402

Table of Contents

Summary of Contents for Texas Instruments TMS320VC5402

Page 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Page 2: Table Of Contents
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Description .........
Page 3 SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 description The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
Page 4 ‡ DV DD is the power supply for the I/O pins while CV DD is the power supply for the core CPU. V SS is the ground for both the I/O pins and the core CPU. The TMS320VC5402PGE (144-pin LQFP) package is footprint-compatible with the ’LC548, ’LC/VC549, and ’VC5410 devices. TMS320VC5402 PGE PACKAGE †‡ (TOP VIEW) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
Page 5 TMS320VC5402GGU (144-pin BGA) package which is footprint-compatible with the ’LC548 and ’LC/VC549 devices. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 TMS320VC5402 GGU PACKAGE (BOTTOM VIEW) 12 11 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
Page 6 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Pin Assignments for the TMS320VC5402GGU (144-Pin BGA) Package SIGNAL SIGNAL BGA BALL # NAME NAME V SS DV DD DV DD V SS CLKMD1 CLKMD2 CLKMD3...
Page 7: Terminal Functions
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions DESCRIPTION DESCRIPTION DATA SIGNALS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402...
Page 8 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 TERMINAL TERMINAL TYPE † TYPE † NAME NAME INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED) Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals.
Page 9 Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) DESCRIPTION DESCRIPTION OSCILLATOR/TIMER SIGNALS MISCELLANEOUS SIGNAL HOST-PORT INTERFACE SIGNALS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402...
Page 10 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 TERMINAL TERMINAL TYPE † TYPE † NAME NAME HOST-PORT INTERFACE SIGNALS (CONTINUED) Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup HBIL resistor that is only enabled when HPIENA = 0.
Page 11 Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) DESCRIPTION DESCRIPTION TEST PINS (CONTINUED) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402...
Page 12: Memory
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory The ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration. on-chip ROM with bootloader The ’5402 features a 4K-word 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the ’5402 programmed with contents unique to any particular application.
Page 13 Reserved FF7F FF80 Interrupts (On-Chip) FFFF FFFF MP/MC= 0 (Microcomputer Mode) Figure 1. Memory Map POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 Data Memory Mapped Registers Scratch-Pad On-Chip DARAM (16K x 16-bit) External ROM (DROM=1) or External (DROM=0) Reserved...
Page 14 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 relocatable interrupt vector table (continued) IPTR LEGEND: R = Read, W = Write Figure 2. Processor Mode Status (PMST) Registers extended program memory The ’5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program memory locations.
Page 15 Page 1 Page 2 Upper Upper External External 2 FFFF Figure 3. Extended Program Memory POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 . . . F 0000 Page 15 Lower . . . 16K} F 3FFF External . . .
Page 16: On-Chip Peripherals
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 on-chip peripherals The ’5402 device has the following peripherals: Software-programmable wait-state generator with programmable bank-switching wait states An enhanced 8-bit host-port interface (HPI8) Two multichannel buffered serial ports (McBSPs)
Page 17 SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 FUNCTION FUNCTION Reserved R/W-0 FUNCTION FUNCTION POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 SWSM R/W-0...
Page 18: Programmable Bank-Switching Wait States
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 programmable bank-switching wait states The programmable bank-switching logic of the ’5402 is functionally equivalent to that of the ’548/’549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space.
Page 19: Parallel I/O Ports
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the ’5402. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402...
Page 20: Multichannel Buffered Serial Ports
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial ports The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other ’54x devices.
Page 21: Hardware Timer
(CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402...
Page 22 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 clock generator (continued) The reference clock input is then divided by two (DIV mode) to generate clocks for the ’5402 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive...
Page 23: Dma Controller
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 0000 Reserved 001F 0020 McBSP Registers 0023 0024 Reserved 005F 0060 Scratch-Pad 007F 0080 (16K x 16-bit) On-Chip DARAM 3FFF 4000 Reserved FFFF Figure 7. ’5402 DMA Memory Map POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402...
Page 24 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA priority level Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple DMA channels that are assigned to the same priority level are handled in a round-robin manner.
Page 25 Table 7. DMA Synchronization Events DMA SYNCHRONIZATION EVENT No synchronization used McBSP0 receive event McBSP0 transmit event Reserved McBSP1 receive event McBSP1 transmit event Reserved Timer0 interrupt External interrupt 3 Timer1 interrupt POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 INTERRUPT...
Page 26 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA channel interrupt selection The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an interrupt line with timer 1 (IMR/IFR bit 7).
Page 27: Memory-Mapped Registers
Auxiliary register 7 Stack pointer register Circular buffer size register Block repeat counter Block repeat start address Block repeat end address Processor mode status (PMST) register Extended program page register Reserved POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 DESCRIPTION DESCRIPTION...
Page 28 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory-mapped registers (continued) Table 10. Peripheral Memory-Mapped Registers NAME ADDRESS DRR20 McBSP0 data receive register 2 DRR10 McBSP0 data receive register 1 DXR20 McBSP0 data transmit register 2...
Page 29: Mcbsp Control Registers And Subaddresses
Multichannel register 1 Multichannel register 2 Receive channel enable register partition A Receive channel enable register partition B Transmit channel enable register partition A Transmit channel enable register partition B Pin control register POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 DESCRIPTION...
Page 30 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA subbank addressed registers (continued) Table 12. DMA Subbank Addressed Registers SUB- NAME ADDRESS ADDRESS DMSRC0 56h/57h DMDST0 56h/57h DMCTR0 56h/57h DMSFC0 56h/57h DMMCR0 56h/57h DMSRC1...
Page 31: Interrupts
— — — — — 78–7F — POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 FUNCTION Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22...
Page 32 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 interrupts (continued) The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 8. 15–14 DMAC5 DMAC4 BXINT1...
Page 33: Documentation Support
TMS320 devices. For general background information on DSPs and Texas Instruments (TI) devices, see the three-volume publication Digital Signal Processing Applications with the TMS320 Family (literature numbers SPRA012, SPRA016, and SPRA017).
Page 34: Absolute Maximum Ratings
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 absolute maximum ratings over specified temperature range (unless otherwise noted) Supply voltage I/O range, DV Supply voltage core range, CV Input voltage range, V .............
Page 35: Electrical Characteristics
1 mode, 100 MHz input Divide-by-two mode, CLKIN stopped I OL V Load I OH Figure 9. 3.3-V Test Load Circuit POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 TYP † UNIT –175 –5 –40 –5 (V I = V SS –5...
Page 36: Internal Oscillator With External Crystal
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 internal oscillator with external crystal The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register.
Page 37: Divide-By-Two Clock Option (Pll Disabled)
Figure 11. External Divide-by-Two Clock Timing FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 t f(CO) t r(CO) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 UNIT † . The device is characterized at frequencies † (see Figure 10, c(CO) UNIT 10 ‡...
Page 38: Multiply-By-N Clock Option
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multiply-by-N clock option The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator section.
Page 39: Memory And Parallel I/O Interface Timing
§ In the case of a memory read preceded by a memory write FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 c(CO) PARAMETER POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 † (see Figure 13) UNIT 2H–7 2H–8 –2 UNIT –2...
Page 40 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) CLKOUT t d(CLKL-A) t h(CLKL-A)R A[19:0] t h(A-D)R t su(D)R t a(A)M t h(D)R D[15:0] t h(D)MSTRBH t d(CLKL-MSL)
Page 41 § In the case of a memory write preceded by an I/O cycle FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 PARAMETER POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 UNIT –2 –2 –1 –1 –1...
Page 42 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) CLKOUT t d(CLKL-A) A[19:0] D[15:0] MSTRB t en(D-RWL) PS, DS NOTE A: A[19:16] are always driven low during accesses to external data space.
Page 43 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 PARAMETER t su(D)IOR t a(A)IO t d(CLKH-ISTRBH) t d(CLKH-ISTRBL) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 † (see Figure 15) c(CO) UNIT 3H–7 2H–7 UNIT –2 –2...
Page 44 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port write † (IOSTRB = 0) [H = 0.5 t...
Page 45: Ready Timing For Externally Generated Wait States
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 t su(RDY) t h(RDY) t h(RDY)MSTRB t v(MSCH) t v(MSCL) Wait States Generated Internally POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 † (see Figure 17, Figure 18, c(CO) UNIT 4H–8 5H–8 –1 –1 Wait State...
Page 46 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 ready timing for externally generated wait states (continued) CLKOUT A[19:0] D[15:0] READY t v(RDY)MSTRB MSTRB NOTE A: A[19:16] are always driven low during accesses to external data space.
Page 47 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 ready timing for externally generated wait states (continued) CLKOUT A[19:0] t h(RDY) t su(RDY) READY t v(RDY)IOSTRB t h(RDY)IOSTRB IOSTRB t v(MSCH) t v(MSCL) Wait State Generated...
Page 48 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 ready timing for externally generated wait states (continued) CLKOUT A[19:0] D[15:0] READY t v(RDY)IOSTRB IOSTRB NOTE A: A[19:16] are always driven low during accesses to I/O space.
Page 49: Hold And Holda Timings
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 ] (see Figure 21) c(CO) UNIT 4H+7 UNIT 2H+5 2H+5 2H+5 –1 –1 2H–1...
Page 50: Reset, Bio, Interrupt, And Mp/Mc Timings
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 reset, BIO, interrupt, and MP/MC timings timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t and Figure 24) t h(RS) Hold time, RS after CLKOUT low...
Page 51 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 reset, BIO, interrupt, and MP/MC timings (continued) X2/CLKIN t su(RS) t w(RSL) RS, INTn, NMI t su(INT) t h(RS) CLKOUT t su(BIO) t h(BIO) t w(BIO)S Figure 22.
Page 52: Instruction Acquisition (Iaq), Interrupt Acknowledge 27 (Iack), External Flag (Xf), And Tout Timings
TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings switching characteristics over recommended operating conditions for IAQ and IACK [H = 0.5 t...
Page 53 TOUT FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 PARAMETER t d(XF) Figure 26. XF Timing t d(TOUTL) t w(TOUT) Figure 27. TOUT Timing POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 UNIT –1 –1...
Page 54: Multichannel Buffered Serial Port Timing
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § The transmit delay enable (DXENA) and A–bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5402.
Page 55 Bit (n–1) (n–2) Bit (n–1) Figure 29. McBSP Transmit Timings POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 t r(BCKRX) t r(BCKRX) (n–3) (n–4) t h(BCKRL–BDRV) (n–2) (n–3) t h(BCKRL–BDRV) Bit (n–1) (n–2)
Page 56 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP general-purpose I/O (see Figure 30) Setup time, BGPIOx input mode before CLKOUT high † t su(BGPIO-COH) Hold time, BGPIOx input mode after CLKOUT high †...
Page 57 Bit(n-1) (n-2) t su(BDRV-BCLXL) t h(BCKXL-BDRV) Bit(n-1) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 ] CLKSTP = 10b, CLKXP = 0 MASTER SLAVE UNIT UNIT – 12H 5 + 12H ] CLKSTP = 10b, c(CO) ‡...
Page 58 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5t (see Figure 32) t su(BDRV-BCKXH) Setup time, BDR valid before BCLKX high...
Page 59 SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 t su(BFXL-BCKXL) t d(BFXL-BCKXL) t d(BFXL-BDXV) Bit(n-1) t su(BDRV-BCKXH) Bit(n-1) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 ] CLKSTP = 10b, CLKXP = 1 c(CO) MASTER SLAVE UNIT UNIT 2 – 12H 5 + 12H...
Page 60 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5t (see Figure 34) t su(BDRV-BCKXL) Setup time, BDR valid before BCLKX low...
Page 61: Hpi8 Timing
Case 2: Memory accesses when DMAC is inactive Case 3: Write accesses to HPIC register (see Note 2) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 †‡§¶ [H = 0.5t c(CO) UNIT 18H+16 – t w(DSH) 26H+16 – t w(DSH) 10H+16 –...
Page 62 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 HPI8 timing (continued) †‡§ timing requirements (see Figure 35, Figure 36, Figure 37, and Figure 38) Setup time, HBIL and HAD valid before DS low or before HAS low ¶# t su(HBV-DSL) Hold time, HBIL and HAD valid after DS low or after HAS low ¶#...
Page 63 SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 First Byte t su(HSL-DSL) t h(DSL-HBV) Valid t h(DSL-HBV) ‡ t w(DSH) t w(DSL) t d(DSH-HYH) t d(DSL-HDV1) Valid t v(HYH-HDV) Valid t d(COH-HYH) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 Second Byte Valid Valid Valid...
Page 64 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 HPI8 timing (continued) Second Byte HRDY Figure 36. Using HCS to Control Accesses CLKOUT HINT CLKOUT GPIOx Input Mode † GPIOx Output Mode † † GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
Page 65: Mechanical Data
FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 MECHANICAL DATA 0,05 MIN Thermal Resistance Characteristics R JA R JC POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS320VC5402 PLASTIC QUAD FLATPACK 0,27 0,08 0,17 0,50 0,13 NOM Gage Plane 0,25 0 –7...
Page 66 TMS320VC5402 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 GGU (S-PBGA-N144) 12,10 11,90 0,95 0,85 0,55 0,12 0,08 0,45 0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
Page 67 www.ti.com PACKAGING INFORMATION Orderable Device Status DSG5402PGE100 ACTIVE TMS320VC5402GGU100 ACTIVE TMS320VC5402GGUR10 ACTIVE TMS320VC5402PGE100 ACTIVE TMS320VC5402PGER10 ACTIVE TMS320VC5402ZGU100 ACTIVE TMS32C5402PGER10G4 ACTIVE TMX320VC5402GGU100 OBSOLETE TMX320VC5402PGE100 OBSOLETE The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs.
Page 68 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
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