Register Bit Used To Enable/Disable The Digital Loopback Mode; Receive Signals Connected To Transmit Signals In Digital Loopback Mode - Texas Instruments TMS320VC5501 Reference Manual

7.5 Enabling/Disabling the Digital Loopback Mode
Figure 7−3. Register Bit Used to Enable/Disable the Digital Loopback Mode
SPCR1
15 14
DLB
R/W-0
Legend: R = Read; W = Write; -n = Value after reset
Table 7−4. Register Bit Used to Enable/Disable the Digital Loopback Mode
Register Bit Name
SPCR1 15 DLB
7.5.1 About the Digital Loopback Mode
Table 7−5. Receive Signals Connected to Transmit Signals in Digital Loopback Mode
SPRU592E
The DLB bit determines whether the digital loopback mode is on. DLB is shown
in Figure 7−3 and described in Table 7−4.
Function
Digital Loopback Mode
DLB = 0 Digital loopback mode is disabled.
DLB = 1 Digital loopback mode is enabled.
In the digital loopback mode, the receive signals are connected internally
through multiplexers to the corresponding transmit signals, as shown in
Table 7−5. This mode allows testing of serial port code with a single DSP
device; the McBSP receives the data it transmits.
This Receive Signal ...
DR (receive data)
FSR (receive frame synchronization)
CLKR (receive clock)
Enabling/Disabling the Digital Loopback Mode
Is Fed Internally By
This Transmit Signal ...
DX (transmit data)
FSX (transmit frame synchronization)
CLKX (transmit clock)
Receiver Configuration
0
7-7