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Related Manuals for Texas Instruments TMS320VC5501
Summary of Contents for Texas Instruments TMS320VC5501
- Page 1 TMS320VC5501/5502 DSP Instruction Cache Reference Guide SPRU630C June 2004...
- Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
- Page 3 About This Manual This manual describes the features and operation of the instruction cache that is available on the TMS320VC5501 and TMS320VC5502 digital signal processors (DSPs) in the TMS320C55x (C55x) DSP generation. This manual assumes the reader has some fundamental knowledge about cache operation.
- Page 4 Related Documentation From Texas Instruments TMS320C55x Technical Overview (literature number SPRU393). This overview is an introduction to the TMS320C55x DSPs, the latest generation of fixed-point DSPs in the TMS320C5000 DSP platform. Like the previous generations, this processor is optimized for high performance and low-power operation.
- Page 5 Trademarks Trademarks TMS320C5000, TMS320C55x, C55x trademarks Texas Instruments. Other trademarks are the property of their respective owners. SPRU630C Instruction Cache...
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Page 7: Table Of Contents
Contents Contents Introduction ............... 2-Way Cache . - Page 8 Figures Figures Conceptual Block Diagram of the I-Cache in the DSP System ......2-Way Cache ..............Fetch Address Fields for the 2-Way Cache .
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Page 9: Introduction
Instruction Cache On the TMS320VC5501/5502 digital signal processors (DSPs), instructions can reside in internal memory or external memory. When instructions reside in external memory, the instruction cache (I-Cache) can improve the overall system performance by buffering the most recent instructions accessed by the central processing unit (CPU). -
Page 10: Conceptual Block Diagram Of The I-Cache In The Dsp System
Introduction Figure 1. Conceptual Block Diagram of the I-Cache in the DSP System VC5501/5502 DSP I-Cache Cache-control bits in Control logic ST3_55 to enable, freeze, and flush I-Cache Data read/write logic I-Cache registers to configure and monitor I-Cache Instruction buffer 2-way cache queue I-Cache... -
Page 11: 2-Way Cache
Introduction TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide ( literature number SPRU621). Since data from the EMIF passes through the IPORT to get to the I−cache, the IPORT must be properly enabled to allow proper cache operation. The IPORTI bit in the Idle Control Register (ICR) controls whether the IPORT is enabled or disabled after an idle instruction. -
Page 12: I-Cache Operation
Introduction Figure 2. 2-Way Cache Memory bank 1 Memory bank 2 Data Data Set 0 Line 0 Line 0 Set 1 Line 1 Line 1 Set 254 Line 254 Line 254 Set 255 Line 255 Line 255 Set 510 Line 510 Line 510 Set 511 Line 511... -
Page 13: How The I-Cache Uses The Fetch Address
Introduction 1.2.1 How the I-Cache Uses the Fetch Address Figure 3 and Table 1 describe how the I-Cache uses the fetch address for the 2-way cache. Figure 3. Fetch Address Fields for the 2-Way Cache 13 12 Index (set) Offset Byte 11 bits 9 bits... -
Page 14: Line Load Process
Introduction Table 2. Instruction Presence Check and I-Cache Response Case 2-Way Cache Presence I-Cache Response Miss False 2-way cache line loaded from external memory, requested 32-bit word delivered to CPU True Requested 32-bit word taken directly from 2-way cache 1.2.3 Line Load Process When an instruction presence check results in a fetch from the external memory, the 4-word external memory block that contains the requested word... -
Page 15: Flow Chart Of The Line Load Process
Introduction Figure 4. Flow Chart of the Line Load Process I-Cache must load 2-way cache line Command EMIF to read four 32-bit words from external memory word received Wait for next word Write word to line it the Line requested load done word Deliver word to... -
Page 16: Cpu Bits For Controlling The I-Cache
CPU Bits for Controlling the I-Cache CPU Bits for Controlling the I-Cache Control of the I-Cache is maintained not only through the I-Cache registers but also through three bits located in status register ST3_55 of the CPU. These bits are highlighted in Figure 5. For more details about ST3_55, see the TMS320C55x DSP CPU Reference Guide (SPRU371). -
Page 17: Cafrz Bit To Freeze The Contents Of The I-Cache
CPU Bits for Controlling the I-Cache CAFRZ Bit to Freeze the Contents of the I-Cache When you write 1 to the cache freeze (CAFRZ) bit of ST3_55, the contents of the I-Cache are locked. Instruction words that were cached prior to the freeze are still accessible in the case of an I-Cache hit, but the data arrays are not updated in response to an I-Cache miss. -
Page 18: Configuring And Enabling The I-Cache
Configuring and Enabling the I-Cache Configuring and Enabling the I-Cache This section gives the procedures for preparing and enabling the I-Cache. The I-Cache registers mentioned in this section are described in section 6 (page 22). The cache enable (CAEN) bit that is used to enable and disable the I-Cache is described in section 2.1 (page 16). -
Page 19: Timing Considerations
Timing Considerations Timing Considerations As the I-Cache fetches and returns 32-bit words requested by the CPU, two key time periods affect the speed of the I-Cache: Hit time Miss penalty Hit Time The hit time is the time required for the I-Cache to deliver the 32-bit requested word to the CPU in the case of a hit (when the word is present in the I-Cache). -
Page 20: Miss Penalty
Timing Considerations Miss Penalty The miss penalty is the time required for the I-Cache to deliver the 32-bit requested word to the CPU in the case of a miss (when the word must be fetched from external memory). In response to a miss, the I-Cache requests four words from the external memory interface (EMIF) to load the appropriate line. -
Page 21: Power, Emulation, And Reset Considerations
Power, Emulation, and Reset Considerations Power, Emulation, and Reset Considerations See the TMS320C5501 Fixed-Point Digital Signal Processor Data Manual (SPRS206) or the TMS320C5502 Fixed-Point Digital Signal Processor Data Manual (SPRS166) for information on power and reset. Emulator Access The software emulator can read the contents of the I-Cache during the debug mode. -
Page 22: Cache Registers
I-Cache Registers I-Cache Registers Control of the I-Cache is maintained through a set of registers within the I-Cache. These registers are accessible at addresses in the I/O space of the DSP. For the addresses, see the TMS320C5501 Fixed-Point Digital Signal Processor Data Manual (SPRS206) or the TMS320C5502 Fixed-Point Digital Signal Processor Data Manual (SPRS166). -
Page 23: I-Cache Global Control Register (Icgc) Bits
I-Cache Registers Table 4. I-Cache Global Control Register (ICGC) Bits Field Description 15−13 Reserved Always write 110b to these reserved bits. FLUSHLINE Flush the cache line specified by the flush line address registers (ICFARH and ICFARL). The line flush starts when a 1 is written to the FLUSHLINE bit. -
Page 24: Flush Line Address Registers (Icfarl And Icfarh)
I-Cache Registers Flush Line Address Registers (ICFARL and ICFARH) The flush line address registers (ICFARL and ICFARH) contain the program address that is used to determine the line to be flushed. When a line flush is initiated (DE3Ch written to ICGC), the I-Cache automatically flushes the line associated with the program address contained in these registers. -
Page 25: Way Miss Counter Register (Icwmc)
I-Cache Registers Way Miss Counter Register (ICWMC) The ICWMC is incremented by 1 for every miss in the 2-way cache. A DSP reset forces ICWMC = 0000h. ICWMC can be loaded with a value in the range 0000h − FFFFh. When ICWMC is read, it is reset to 0000h. When it reaches FFFFh, the incrementing stops and ICWMC holds the value FFFFh until the register is read or loaded with a different value. - Page 26 This page is intentionally left blank. Instruction Cache SPRU630C...
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Page 27: Revision History
Revision History This document was revised to SPRU630C from SPRU630B, which was released in August 2003. Changes that were made since the last revision are listed in the following table. Page Additions/Modifications/Deletions Added IPORT block to Figure 1. Revised paragraphs 2 − 4 in Section 1. 10 and 11 Added bit number 12 in Figure 3. - Page 28 This page is intentionally left blank. Instruction Cache SPRU630C...
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Page 29: Index
Index Index 2−way cache, 11 emulator access, 21 enable I−Cache as part of initialization procedure, 18 block diagram of I−Cache, 10 CAEN bit description, 16 external memory interface EMIF, 10 cache clear bit (CACLR) described, 16 fetch address, how I−Cache uses, 13 shown in figure, 16 flush I−Cache, 16 cache control bits of CPU, 16... - Page 30 Index instruction cache (I-Cache), 10 instruction presence check, 13 introduction to I−Cache, 9 operation of I−Cache, 12 IPORT, 10 presence check, 13 LAH bits of ICFARH described in table, 24 shown in figure, 24 LAL bits of ICFARL reconfiguration of I−Cache after DSP reset, 21 described in table, 24 registers of I−Cache, 22 shown in figure, 24...