Typical Spi Interface - Texas Instruments TMS320VC5501 Reference Manual

SPI Protocol
6.1 SPI Protocol
Figure 6−1. Typical SPI Interface
6-2 SPI Operation Using the Clock Stop Mode
The SPI protocol is a master-slave configuration with one master device and
one or more slave devices. The interface consists of the following four signals:
Serial data input (also referred to as Master In − Slave Out, or MISO)
-
Serial data output (also referred to as Master Out − Slave In, or MOSI)
-
Shift-clock (also referred to as SCK)
-
Slave-enable signal (also referred to as SS)
-
A typical SPI interface with a single slave device is shown in Figure 6−1.
SPI-compliant
master
The master device controls the flow of communication by providing shift-clock
and slave-enable signals. The slave-enable signal is an optional active-low
signal that enables the serial data input and output of the slave device (the
device not sending out the clock).
In the absence of a dedicated slave-enable signal, communication between
the master and slave is determined by the presence or absence of an active
shift-clock. When the McBSP is operating in SPI master mode and the SS
signal is not used by the slave SPI port, the slave device must remain enabled
at all times, and multiple slaves cannot be used.
SPI-compliant
slave
SCK
SCK
MOSI
MOSI
MISO
MISO
SS
SS
SPRU592E