Nintendo GAME BOY Programming Manual page 29

Chapter 1: System
When the shift clock goes low, the contents of the SB register are shifted leftward and the data is
output from the highest bit. When the shift clock goes high, input data from the SIN terminal are
output to the lowest bit of the SB register.
When the SCK terminal is in external-clock mode, it is pulled up to VDD.
If the highest bit of the SC register (SC7) is set, reading and writing to the SB register is prohibited.
An SIO serial transfer should be started (highest SC bit set) after the external or internal shift clock
is selected. Excessive shifting may result if the transfer is started before or at the same time as
the shift clock is selected.
If a transfer is performed using the external clock, the data is first set in the SB register, then the
SC register start flag is set and input from the external clock is awaited. The transfer start flag
must be set each time data is transferred.
The maximum setting for an external clock is 500 KHz.
Serial communication (SIO) specifications are essentially the same for DMG and CGB. In CGB,
however, the operating speed of the internal shift clock can be set to high by specifying a speed
in bit 1.
SIO Timing Chart
4 5 6 7 8
1 2 3
SCK
SOUT SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
SIN
7 6 5 4 3 2 1 0
Read Timing
SB
Output Timing
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