Programming Cautions Regarding Mbcs; All Mbcs; Mbc3 - Nintendo GAME BOY Programming Manual

Game Boy Programming Manual

3. PROGRAMMING CAUTIONS REGARDING MBCS

3.1 All MBCs

3.1.1 Protecting RAM Data (Recommended)
To protect RAM data, access to RAM should be disabled (RAMG←00h) when it is not being
accessed.

3.2 MBC3

3.2.1 Accessing the Clock Counters (Required)
If the clock counters themselves are counted up, accessing of the clock counters by the CPU is
performed asynchronously. However, if these operations are performed simultaneously, the clock
counters may fail. To prevent this, MBC3 provides an interface circuit for WR signals from the
CPR. Use of this circuit necessitates a delay when accessing control register 3 and the clock
counter registers (RTC_S, RTC_M, RTC_H, RTC_DL, and RTC_DH). Thus, whenever accessing
these registers consecutively, interpose a delay of 4 cycles between accesses.
When reading clock counter data:
•
Latch all clock counter data using control register 3.
•
Read the data in the clock counter registers.
When writing values to the clock counters:
•
Set data in clock counter register RTC_S.
•
Set data in clock counter register RTC_M.
•
Set data in clock counter register RTC_H.
•
Set data in clock counter register RTC_DL.
•
Set data in clock counter register RTC_DH.
4-cycle delay required
4-cycle delay required
4-cycle delay required
4-cycle delay required
4-cycle delay required
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