Nintendo DMG-01 - Game Boy Console Manual
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Nintendo DMG-01 - Game Boy Console Manual

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TM
Game Boy
CPU Manual
Sources by: Pan of Anthrox, GABY, Marat Fayzullin,
Pascal Felber, Paul Robson, Martin Korth, kOOPa, Bowser
Contents:
Assembly Language Commands, Timings and Opcodes, and
everything you always wanted to know about GB but were
afraid to ask.
THIS DOCUMENT IS PRINTED ON DIN A5 SIZE PAPER
(148mm x 210mm)!
TM
TM
TM
Note: Game Boy
, Game Boy Pocket
, Super Game Boy
and Game
TM
Boy Color
are registered trademarks of Nintendo CO., LTD.
© 1989 to 1999 by Nintendo CO., LTD.
Version: 1.01 by DP

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Summary of Contents for Nintendo DMG-01 - Game Boy Console

  • Page 1 THIS DOCUMENT IS PRINTED ON DIN A5 SIZE PAPER (148mm x 210mm)! Note: Game Boy , Game Boy Pocket , Super Game Boy and Game Boy Color are registered trademarks of Nintendo CO., LTD. © 1989 to 1999 by Nintendo CO., LTD. Version: 1.01 by DP...

  • Page 2: Table Of Contents

    1. Foreword Game Boy CPU Manual Table of Contents 1. Foreword...........4 2. Hardware specifications......5 2.1. Forward:........5 2.2. Terms..........5 2.3. Game Boy Specs.........6 2.4. Processor........6 2.5. Memory Map........8 2.5.1. General memory map......8 2.5.2. Echo of 8kB Internal RAM....9 2.5.3. User I/O........9 2.5.4.
  • Page 3 Game Boy CPU Manual 1. Foreword 3. Game Boy command overview......61 3.1. Foreword........61 3.2. CPU Registers.........61 3.2.1. Generally.........61 3.2.2. Flag Register......62 3.2.3. Program Counter......63 3.2.4. Stack Pointer......63 3.3. Commands........65 3.3.1. 8-Bit Loads.......65 3.3.2. 16-Bit Loads......76 3.3.3. 8-Bit ALU.........80 3.3.4. 16-Bit Arithmetic......90 3.3.5.

  • Page 4: Foreword

    ASM command and the. This can be found in paragraph 2. The third is a summary of specifications and commands for Nintendo Super Game Boy speciffic programming by kOOPa and Bowser. See paragraph 3. Information on how to get your emulator proved programs run on a real Game Boy can be found in the Appendix (thanks to kOOPa).

  • Page 5: Hardware Specifications

    Game Boy, manufactured and designed by Nintendo Co., LTD. This info is presented to inform a user on how their Game Boy works and what makes it "tick". GameBoy is copyrighted by Nintendo Co., LTD.

  • Page 6: Game Boy Specs

    • Power: DC6V 0.7W (DC3V 0.7W for GB Pocket) • Nintendo documents describe the CPU & instructions speed in machine cycles while this document describes them in clock cycles. Here is the translation: 1 machine cycle = 4 clock cycles...
  • Page 7 Game Boy CPU Manual 2.4. Processor have been added and some have been taken away. The following are added instructions: SP,nn ;nn = signed byte (HL),A ;Write A to (HL) and increment HL (HL),A ;Write A to (HL) and decrement HL A,(HL) ;Write (HL) to A and increment HL A,(HL)

  • Page 8: Memory Map

    2.5. Memory Map Game Boy CPU Manual 2.5. Memory Map 2.5.1. General memory map Interrupt Enable Register --------------------------- FFFF Internal RAM --------------------------- FF80 Empty but unusable for I/O --------------------------- FF4C I/O ports --------------------------- FF00 Empty but unusable for I/O --------------------------- FEA0 Sprite Attrib Memory (OAM) --------------------------- FE00 Echo of 8kB Internal RAM...

  • Page 9: Echo Of 8Kb Internal Ram

    Game Boy CPU Manual 2.5.2. Echo of 8kB Internal RAM 2.5.2. Echo of 8kB Internal RAM The addresses E000-FE00 appear to access the internal RAM the same as C000-DE00. (i.e. If you write a byte to address E000 it will appear at C000 and E000. Similarly, writing a byte to C000 will appear at C000 and E000.) 2.5.3.

  • Page 10: Reserved Memory Locations

    2.5.4. Reserved Memory Locations Game Boy CPU Manual 2.5.4. Reserved Memory Locations 0000 Restart $00 Address (RST $00 calls this address.) 0008 Restart $08 Address (RST $08 calls this address.) 0010 Restart $10 Address (RST $10 calls this address.) 0018 Restart $18 Address (RST $18 calls this address.) 0020...
  • Page 11 2.5.4. Reserved Memory Locations 0104-0133 Scrolling Nintendo graphic: CE ED 66 66 CC 0D 00 0B 03 73 00 83 00 0C 00 0D 00 08 11 1F 88 89 00 0E DC CC 6E E6 DD DD D9 99...
  • Page 12 2.5.4. Reserved Memory Locations Game Boy CPU Manual F-ROM+MBC3+TIMER+BATT FF - Hudson HuC-1 10-ROM+MBC3+TIMER+RAM+BATT 11-ROM+MBC3 0148 ROM size: 0 - 256Kbit = 32KByte = 2 banks 1 - 512Kbit = 64KByte = 4 banks 1Mbit = 128KByte = 8 banks 2Mbit = 256KByte = 16 banks 4Mbit = 512KByte =...

  • Page 13: Cartridge Types

    Game Boy CPU Manual 2.5.4. Reserved Memory Locations 014D Complement check (PROGRAM WON'T RUN ON GB IF NOT CORRECT!!!) (It will run on Super GB, however, if incorrect.) 014E-014F Checksum (higher byte first) produced by adding all bytes of a cartridge except for two checksum bytes and taking two lower bytes of the result.
  • Page 14 RAM bank operations write any value but XXXX1010 into 0000-1FFF area. Disabling a RAM bank probably protects that bank from false writes during power down of the GameBoy. (NOTE: Nintendo suggests values $0A to enable and $00 to disable RAM bank!!)
  • Page 15 Game Boy CPU Manual 2.6. Cartridge Types RAM which is in the controller itself. It still requires an external battery to save data during power-off though. The least significant bit of the upper address byte must be zero to enable/disable cart RAM. For example the following addresses can be used to enable/disable cart RAM: 0000-00FF, 0200-02FF, 0400-04FF, ..., 1E00-1EFF.
  • Page 16 2.6. Cartridge Types Game Boy CPU Manual It is similar to the MBC3 (but no RTC) but can access up to 64mbits of ROM and up to 1mbit of RAM. The lower 8 bits of the 9-bit rom bank select is written to the 2000-2FFF area while the upper bit is written to the least significant bit of the 3000-3FFF area.

  • Page 17: Special Modi

    $104 to $133 and place this graphic of a Nintendo logo on the screen at the top. This image is then scrolled until it is in the middle of the screen.
  • Page 18 2.7.1. Power Up Sequence Game Boy CPU Manual BC=$0013 DE=$00D8 HL=$014D Stack Pointer=$FFFE [$FF05] = $00 ; TIMA [$FF06] = $00 ; TMA [$FF07] = $00 ; TAC [$FF10] = $80 ; NR10 [$FF11] = $BF ; NR11 [$FF12] = $F3 ;...

  • Page 19: Stop Mode

    Game Boy CPU Manual 2.7.1. Power Up Sequence It is not a good idea to assume the above values will always exist. A later version GameBoy could contain different values than these at reset. Always set these registers on reset rather than assume they are as above.
  • Page 20 2.7.3. Low-Power Mode Game Boy CPU Manual is executed. If interrupts are disabled (DI) then halt doesn't suspend operation but it does cause the program counter to stop counting for one instruction on the GB,GBP, and SGB as mentioned below. Depending on how much CPU time is required by a game, the HALT instruction can extend battery life anywhere from 5 to 50% or possibly more.
  • Page 21 Game Boy CPU Manual 2.7.3. Low-Power Mode FA FA 34 a,(34FA) (de),a 3) Finally an interesting side effect halt halt This combination hangs the cpu. The first HALT causes the second HALT to be repeated, which therefore causes the following command (=itself) to be repeated - again and again.

  • Page 22: Video

    2.7.3. Low-Power Mode Game Boy CPU Manual ; **** V-Blank Interrupt Routine **** Vblnk: push push push push call SpriteDma ; Do sprite updates (VblnkFlag),a reti 2.8. Video 2.8.1. Tiles The main GameBoy screen buffer (background) consists of 256x256 pixels or 32x32 tiles (8x8 pixels each). Only 160x144 pixels can be displayed on the screen.
  • Page 23 Game Boy CPU Manual 2.8.1. Tiles number of a tile to be displayed. Tile patterns are taken from the Tile Data Table located either at $8000-8FFF or $8800-97FF. In the first case, patterns are numbered with unsigned numbers from 0 to 255 (i.e. pattern #0 lies at address $8000).
  • Page 24 2.8.1. Tiles Game Boy CPU Manual WX may be changed during a scan line interrupt (to either cause a graphic distortion effect or to disable the window (WX>166) ) but changes to WY are not dynamic and won't be noticed until the next screen redraw.

  • Page 25: Sprites

    Game Boy CPU Manual 2.8.2. Sprites 2.8.2. Sprites GameBoy video controller can display up to 40 sprites either in 8x8 or in 8x16 pixels. Because of a limitation of hardware, only ten sprites can be displayed per scan line. Sprite patterns have the same format as tiles, but they are taken from the Sprite Pattern Table located at $8000-8FFF and have unsigned numbering.
  • Page 26 2.8.2. Sprites Game Boy CPU Manual To display a sprite in the upper left corner of the screen set sprite X=8, Y=16. Only 10 sprites can be displayed on any one line. When this limit is exceeded, the lower priority sprites (priorities listed above) won't be displayed.

  • Page 27: Sprite Ram Bug

    Game Boy CPU Manual 2.8.2. Sprites Bit4 Palette number Sprite colors are taken from OBJ1PAL if this bit is set to 1 and from OBJ0PAL otherwise. 2.8.3. Sprite RAM Bug There is a flaw in the GameBoy hardware that causes trash to be written to OAM RAM if the following commands are used while their 16-bit content is in the range of $FE00 to $FEFF:...

  • Page 28: Sound

    2.9. Sound Game Boy CPU Manual 2.9. Sound There are two sound channels connected to the output terminals SO1 and SO2. There is also a input terminal Vin connected to the cartridge. It can be routed to either of both output terminals. GameBoy circuitry allows producing sound in four different ways: Quadrangular wave patterns with sweep and envelope functions.
  • Page 29 Game Boy CPU Manual 2.9. Sound When the All Sound OFF flag (bit 7 of NR52) is set to 0, the mode registers for sounds 1,2,3, and 4 are reset and the sound output stops. (NOTE: The setting of each sounds mode register must be done after the All Sound OFF mode is cancelled.

  • Page 30: Timer

    2.10. Timer Game Boy CPU Manual 2.10. Timer Sometimes it's useful to have a timer that interrupts at regular intervals for routines that require periodic or percise updates. The timer in the GameBoy has a selectable frequency of 4096, 16384, 65536, or 262144 Hertz.

  • Page 31: Serial I/O

    Game Boy CPU Manual 2.11. Serial I/O 2.11. Serial I/O The serial I/O port on the Gameboy is a very simple setup and is crude compared to standard RS-232 (IBM- PC) or RS-485 (Macintosh) serial ports. There are no start or stop bits so the programmer must be more creative when using this port.

  • Page 32: Interrupts

    2.11. Serial I/O Game Boy CPU Manual allows a certain amount of synchronization with each serial port. The state of the last bit shifted out determines the state of the output line until another transfer takes place. If a serial transfer with internal clock is performed and no external GameBoy is present, a value of $FF will be received in the transfer.
  • Page 33 Game Boy CPU Manual 2.12.1. Interrupt Procedure Resetting of the IF register, which was the cause of the interrupt, is done by hardware. During the interrupt, pushing of registers to be used should be performed by the interrupt routine. Once the interrupt service is in progress, all the interrupts will be prohibited.

  • Page 34: Interrupt Descriptions

    2.12.2. Interrupt Descriptions Game Boy CPU Manual 2.12.2. Interrupt Descriptions The following interrupts only occur if they have been enabled in the Interrupt Enable register ($FFFF) and if the interrupts have actually been enabled using the EI instruction. 1. V-Blank The V-Blank interrupt occurs ~59.7 times a second on a regular GB and ~61.1 times a second on a Super GB (SGB).

  • Page 35: Special Registers

    Game Boy CPU Manual 2.12.2. Interrupt Descriptions 5. High-to-Low of P10-P13 This interrupt occurs on a transition of any of the keypad input lines from high to low. Due to the fact that keypad "bounce"* is virtually always present, software should expect this interrupt to occur one or more times for every button press and one or more times for every button release.
  • Page 36 2.13.1. I/O Registers Game Boy CPU Manual This is the matrix layout for register $FF00: P10-------O-Right----O-A P11-------O-Left-----O-B P12-------O-Up-------O-Select P13-------O-Down-----O-Start Example code: Game: Ms. Pacman Address: $3b1 LD A,$20 <- bit 5 = $20 LD ($FF00),A <- select P14 by setting it low LD A,($FF00) LD A,($FF00) <- wait a few cycles...
  • Page 37 Game Boy CPU Manual 2.13.1. I/O Registers <- complement (invert) AND $0F <- get first 4 bits OR B <- put A and B together LD B,A <- store A in D LD A,($FF8B) <- read old joy data from ram XOR B <- toggle w/current button bit AND B...
  • Page 38 2.13.1. I/O Registers Game Boy CPU Manual Bit 7 - Transfer Start Flag 0: Non transfer 1: Start transfer Bit 0 - Shift Clock 0: External Clock (500KHz Max.) 1: Internal Clock (8192Hz) Transfer is initiated by setting the Transfer Start Flag. This bit may be read and is automatically set to 0 at the end of Transfer.
  • Page 39 Game Boy CPU Manual 2.13.1. I/O Registers 6. FF06 (TMA) Name - TMA Contents - Timer Modulo (R/W) When the TIMA overflows, this data will be loaded. 7. FF07 (TAC) Name - TAC Contents - Timer Control (R/W) Bit 2 - Timer Stop 0: Stop Timer 1: Start Timer Bits 1+0 - Input Clock Select...
  • Page 40 2.13.1. I/O Registers Game Boy CPU Manual interrupts are: Interrupt Priority Start Address V-Blank $0040 LCDC Status $0048 - Modes 0, 1, 2 LYC=LY coincide (selectable) Timer Overflow $0050 Serial Transfer $0058 - when transfer is complete Hi-Lo of P10-P13 $0060 * When more than 1 interrupts occur at the same time only the interrupt with the highest priority...
  • Page 41 Game Boy CPU Manual 2.13.1. I/O Registers 100: 31.3 ms (4/128Hz) 101: 39.1 ms (5/128Hz) 110: 46.9 ms (6/128Hz) 111: 54.7 ms (7/128Hz) The change of frequency (NR13,NR14) at each shift is calculated by the following formula where X(0) is initial freq & X(t- 1) is last freq: X(t) = X(t-1) +/- X(t-1)/2^n 10.
  • Page 42 2.13.1. I/O Registers Game Boy CPU Manual 11. FF12 (NR12) Name - NR 12 Contents - Sound Mode 1 register, Envelope (R/W) Bit 7-4 - Initial volume of envelope Bit 3 - Envelope UP/DOWN 0: Attenuate 1: Amplify Bit 2-0 - Number of envelope sweep (n: 0-7) (If zero, stop envelope operation.) Initial volume of envelope is from 0 to...
  • Page 43 Game Boy CPU Manual 2.13.1. I/O Registers Bit 2-0 - Frequency's higher 3 bits (x) Frequency = 4194304/(32*(2048-x)) Hz = 131072/(2048-x) Hz Counter/consecutive Selection 0 = Regardless of the length data in NR11 sound can be produced consecutively. 1 = Sound is generated during the time period set by the length data in NR11.
  • Page 44 2.13.1. I/O Registers Game Boy CPU Manual 15. FF17 (NR 22) Name - NR 22 Contents - Sound Mode 2 register, envelope (R/W) Bit 7-4 - Initial volume of envelope Bit 3 - Envelope UP/DOWN 0: Attenuate 1: Amplify Bit 2-0 - Number of envelope sweep (n: 0-7) (If zero, stop envelope operation.) Initial volume of envelope is from 0 to...
  • Page 45 Game Boy CPU Manual 2.13.1. I/O Registers restarts) Bit 6 - Counter/consecutive selection Bit 2-0 - Frequency's higher 3 bits (x) Frequency = 4194304/(32*(2048-x)) Hz = 131072/(2048-x) Hz Counter/consecutive Selection 0 = Regardless of the length data in NR21 sound can be produced consecutively.
  • Page 46 2.13.1. I/O Registers Game Boy CPU Manual 20. FF1C (NR 32) Name - NR 32 Contents - Sound Mode 3 register, Select output level (R/W) Only bits 6-5 can be read Bit 6-5 - Select output level 00: Mute 01: Produce Wave Pattern RAM Data as it is(4 bit length) 10: Produce Wave Pattern RAM data shifted once to the...
  • Page 47 Game Boy CPU Manual 2.13.1. I/O Registers Bit 7 - Initial (when set,sound restarts) Bit 6 - Counter/consecutive flag Bit 2-0 - Frequency's higher 3 bits (x). Frequency = 4194304/(64*(2048-x)) Hz = 65536/(2048-x) Hz Counter/consecutive Selection 0 = Regardless of the length data in NR31 sound can be produced consecutively.
  • Page 48 2.13.1. I/O Registers Game Boy CPU Manual Bit 2-0 - Number of envelope sweep (n: 0-7) (If zero, stop envelope operation.) Initial volume of envelope is from 0 to $F. Zero being no sound. Length of 1 step = n*(1/64) seconds 25.
  • Page 49 Game Boy CPU Manual 2.13.1. I/O Registers Selection of the shift clock frequency of the polynomial counter: 0000: dividing ratio of frequencies * 1/2 0001: dividing ratio of frequencies * 1/2^2 0010: dividing ratio of frequencies * 1/2^3 0011: dividing ratio of frequencies * 1/2^4 0101: dividing ratio of frequencies * 1/2^14 1110: prohibited code 1111: prohibited code...
  • Page 50 2.13.1. I/O Registers Game Boy CPU Manual 27. FF24 (NR 50) Name - NR 50 Contents - Channel control / ON-OFF / Volume (R/W) Bit 7 - Vin->SO2 ON/OFF Bit 6-4 - SO2 output level (volume) (# 0-7) Bit 3 - Vin->SO1 ON/OFF Bit 2-0 - SO1 output level (volume) (# 0-7) Vin->SO1 (Vin->SO2) By synthesizing the sound from sound 1...
  • Page 51 Game Boy CPU Manual 2.13.1. I/O Registers 29. FF26 (NR 52) Name - NR 52 (Value at reset: $F1-GB, $F0-SGB) Contents - Sound on/off (R/W) Bit 7 - All sound on/off 0: stop all sound circuits 1: operate all sound circuits Bit 3 - Sound 4 ON flag Bit 2 - Sound 3 ON flag Bit 1 - Sound 2 ON flag...
  • Page 52 2.13.1. I/O Registers Game Boy CPU Manual 0: Stop completely (no picture on screen) 1: operation Bit 6 - Window Tile Map Display Select 0: $9800-$9BFF 1: $9C00-$9FFF Bit 5 - Window Display 0: off 1: on Bit 4 - BG & Window Tile Data Select 0: $8800-$97FF 1: $8000-$8FFF <- Same area as OBJ Bit 3 - BG Tile Map Display Select...
  • Page 53 Game Boy CPU Manual 2.13.1. I/O Registers Bit 6 - LYC=LY Coincidence (Selectable) Bit 5 - Mode 10 Bit 4 - Mode 01 Bit 3 - Mode 00 0: Non Selection 1: Selection Bit 2 - Coincidence Flag 0: LYC not equal to LCDC LY 1: LYC = LCDC LY Bit 1-0 - Mode Flag 00: During H-Blank...
  • Page 54 2.13.1. I/O Registers Game Boy CPU Manual Mode 0: 000___000___000___000___000___000___000________________ Mode 1: _______________________________________11111111111111__ Mode 2: ___2_____2_____2_____2_____2_____2___________________2_ Mode 3: ____33____33____33____33____33____33__________________3 The Mode Flag goes through the values 0, 2, and 3 at a cycle of about 109uS. 0 is present about 48.6uS, 2 about 19uS, and 3 about 41uS. This is interrupted every 16.6ms by the VBlank (1).
  • Page 55 Game Boy CPU Manual 2.13.1. I/O Registers 34. FF43 (SCX) Name - SCX Contents - Scroll X (R/W) 8 Bit value $00-$FF to scroll BG X screen position. 35. FF44 (LY) Name - LY Contents - LCDC Y-Coordinate (R) The LY indicates the vertical line to which the present data is transferred to the LCD Driver.
  • Page 56 2.13.1. I/O Registers Game Boy CPU Manual can be performed. It takes 160 microseconds for the transfer. 40*28 bit = #140 or #$8C. As you can see, it only transfers $8C bytes of data. OAM data is $A0 bytes long, from $0-$9F. But if you examine the OAM data you see that 4 bits are not in use.
  • Page 57 Game Boy CPU Manual 2.13.1. I/O Registers org $ff80 VBlank: push af <- Save A reg & flags ld a,BASE_ADRS <- transfer data from BASE_ADRS ld ($ff46),a <- put A into DMA registers ld a,28h <- loop length Wait: <- We need to wait 160 ms. dec a <- 4 cycles - decrease A by 1...
  • Page 58 2.13.1. I/O Registers Game Boy CPU Manual 39. FF48 (OBP0) Name - OBP0 Contents - Object Palette 0 Data (R/W) This selects the colors for sprite palette 0. It works exactly as BGP ($FF47) except each each value of 0 is transparent.
  • Page 59 Game Boy CPU Manual 2.13.1. I/O Registers must be less than or equal to 166 for window to be visible. WX is offset from absolute screen coordinates by 7. Setting the window to WX=7, WY=0 will put the upper left corner of the window at absolute screen coordinates 0,0.
  • Page 60 2.13.1. I/O Registers Game Boy CPU Manual 43. FFFF (IE) Name - IE Contents - Interrupt Enable (R/W) Bit 4: Transition from High to Low of Pin number P10-P13. Bit 3: Serial I/O transfer complete Bit 2: Timer Overflow Bit 1: LCDC (see STAT) Bit 0: V-Blank 0: disable 1: enable...

  • Page 61: Game Boy Command Overview

    Game Boy CPU Manual 3. Game Boy command overview 3. Game Boy command overview 3.1. Foreword Since books on the Z80 are getting harder & harder to find, hopefully the information here might be helpful to those trying to understand assembly language specific to GameBoy.

  • Page 62: Flag Register

    3.2.1. Generally Game Boy CPU Manual programmer and is used to store the results of various math operations. The PC, or Program Counter, register points to the next instruction to be executed in the Game Boy memory. The SP, or Stack Pointer, register points to the current stack position.

  • Page 63: Program Counter

    Game Boy CPU Manual 3.2.3. Program Counter 3.2.3. Program Counter On power up, the GameBoy Program Counter is initialized to $100 (100 hex) and the instruction found at this location in ROM is executed. The Program Counter from this point on is controlled, indirectly, by the program instructions themselves that were generated by the programmer of the ROM cart.
  • Page 64 3.2.4. Stack Pointer Game Boy CPU Manual command LD SP,$E000. (The Stack Pointer automatically decrements before it puts something onto the stack so it is perfectly acceptable to assign it a value which points to a memory address which is one location past the end of available RAM.) The GameBoy stack pointer is initialized to $FFFE on power up but a programmer should not rely on this...

  • Page 65: Commands

    Game Boy CPU Manual 3.3. Commands 3.3. Commands The GameBoy CPU is based on a subset of the Z80 micro- processor. A summary of these commands is given below. If 'Flags affected' is not given for a command then none are affected. 3.3.1.
  • Page 66 3.3.1. 8-Bit Loads Game Boy CPU Manual 2. LD r1,r2 Description: Put value r2 into r1. Use with: r1,r2 = A,B,C,D,E,H,L,(HL) Opcodes: Instruction Parameters Opcode Cycles A,(HL) B,(HL) C,(HL) Page 66 V 1.01...
  • Page 67 Game Boy CPU Manual 3.3.1. 8-Bit Loads D,(HL) E,(HL) H,(HL) L,(HL) (HL),B (HL),C (HL),D (HL),E (HL),H (HL),L (HL),n by DP Page 67...
  • Page 68 3.3.1. 8-Bit Loads Game Boy CPU Manual 3. LD A,n Description: Put value n into A. Use with: n = A,B,C,D,E,H,L,(BC),(DE),(HL),(nn),# nn = two byte immediate value. (LS byte first.) Opcodes: Instruction Parameters Opcode Cycles A,(BC) A,(DE) A,(HL) A,(nn) Page 68 V 1.01...
  • Page 69 Game Boy CPU Manual 3.3.1. 8-Bit Loads 4. LD n,A Description: Put value A into n. Use with: n = A,B,C,D,E,H,L,(BC),(DE),(HL),(nn) nn = two byte immediate value. (LS byte first.) Opcodes: Instruction Parameters Opcode Cycles (BC),A (DE),A (HL),A (nn),A by DP Page 69...
  • Page 70 3.3.1. 8-Bit Loads Game Boy CPU Manual 5. LD A,(C) Description: Put value at address $FF00 + register C into A. Same as: LD A,($FF00+C) Opcodes: Instruction Parameters Opcode Cycles A,(C) 6. LD (C),A Description: Put A into address $FF00 + register C. Opcodes: Instruction Parameters...
  • Page 71 Game Boy CPU Manual 3.3.1. 8-Bit Loads 7. LD A,(HLD) Description: Same as: LDD A,(HL) 8. LD A,(HL-) Description: Same as: LDD A,(HL) 9. LDD A,(HL) Description: Put value at address HL into A. Decrement HL. Same as: LD A,(HL) - DEC HL Opcodes: Instruction Parameters...
  • Page 72 3.3.1. 8-Bit Loads Game Boy CPU Manual 10. LD (HLD),A Description: Same as: LDD (HL),A 11. LD (HL-),A Description: Same as: LDD (HL),A 12. LDD (HL),A Description: Put A into memory address HL. Decrement HL. Same as: LD (HL),A - DEC HL Opcodes: Instruction Parameters...
  • Page 73 Game Boy CPU Manual 3.3.1. 8-Bit Loads 13. LD A,(HLI) Description: Same as: LDI A,(HL) 14. LD A,(HL+) Description: Same as: LDI A,(HL) 15. LDI A,(HL) Description: Put value at address HL into A. Increment HL. Same as: LD A,(HL) - INC HL Opcodes: Instruction Parameters...
  • Page 74 3.3.1. 8-Bit Loads Game Boy CPU Manual 16. LD (HLI),A Description: Same as: LDI (HL),A 17. LD (HL+),A Description: Same as: LDI (HL),A 18. LDI (HL),A Description: Put A into memory address HL. Increment HL. Same as: LD (HL),A - INC HL Opcodes: Instruction Parameters...
  • Page 75 Game Boy CPU Manual 3.3.1. 8-Bit Loads 19. LDH (n),A Description: Put A into memory address $FF00+n. Use with: n = one byte immediate value. Opcodes: Instruction Parameters Opcode Cycles ($FF00+n),A 20. LDH A,(n) Description: Put memory address $FF00+n into A. Use with: n = one byte immediate value.

  • Page 76: 16-Bit Loads

    3.3.2. 16-Bit Loads Game Boy CPU Manual 3.3.2. 16-Bit Loads 1. LD n,nn Description: Put value nn into n. Use with: n = BC,DE,HL,SP nn = 16 bit immediate value Opcodes: Instruction Parameters Opcode Cycles BC,nn DE,nn HL,nn SP,nn 2. LD SP,HL Description: Put HL into Stack Pointer (SP).
  • Page 77 Game Boy CPU Manual 3.3.2. 16-Bit Loads 3. LD HL,SP+n Description: Same as: LDHL SP,n. 4. LDHL SP,n Description: Put SP + n effective address into HL. Use with: n = one byte signed immediate value. Flags affected: Z - Reset. N - Reset.
  • Page 78 3.3.2. 16-Bit Loads Game Boy CPU Manual 5. LD (nn),SP Description: Put Stack Pointer (SP) at address n. Use with: nn = two byte immediate address. Opcodes: Instruction Parameters Opcode Cycles (nn),SP 6. PUSH nn Description: Push register pair nn onto stack. Decrement Stack Pointer (SP) twice.
  • Page 79 Game Boy CPU Manual 3.3.2. 16-Bit Loads 7. POP nn Description: Pop two bytes off stack into register pair nn. Increment Stack Pointer (SP) twice. Use with: nn = AF,BC,DE,HL Opcodes: Instruction Parameters Opcode Cycles by DP Page 79...

  • Page 80: 8-Bit Alu

    3.3.3. 8-Bit ALU Game Boy CPU Manual 3.3.3. 8-Bit ALU 1. ADD A,n Description: Add n to A. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. N - Reset. H - Set if carry from bit 3. C - Set if carry from bit 7.
  • Page 81 Game Boy CPU Manual 3.3.3. 8-Bit ALU 2. ADC A,n Description: Add n + Carry flag to A. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. N - Reset. H - Set if carry from bit 3. C - Set if carry from bit 7.
  • Page 82 3.3.3. 8-Bit ALU Game Boy CPU Manual 3. SUB n Description: Subtract n from A. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. N - Set. H - Set if no borrow from bit 4. C - Set if no borrow.
  • Page 83 Game Boy CPU Manual 3.3.3. 8-Bit ALU 4. SBC A,n Description: Subtract n + Carry flag from A. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. N - Set. H - Set if no borrow from bit 4. C - Set if no borrow.
  • Page 84 3.3.3. 8-Bit ALU Game Boy CPU Manual 5. AND n Description: Logically AND n with A, result in A. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. N - Reset. H - Set. C - Reset. Opcodes: Instruction Parameters...
  • Page 85 Game Boy CPU Manual 3.3.3. 8-Bit ALU 6. OR n Description: Logical OR n with register A, result in A. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Reset.
  • Page 86 3.3.3. 8-Bit ALU Game Boy CPU Manual 7. XOR n Description: Logical exclusive OR n with register A, result in A. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Reset.
  • Page 87 Game Boy CPU Manual 3.3.3. 8-Bit ALU 8. CP n Description: Compare A with n. This is basically an A - n subtraction instruction but the results are thrown away. Use with: n = A,B,C,D,E,H,L,(HL),# Flags affected: Z - Set if result is zero. (Set if A = n.) N - Set.
  • Page 88 3.3.3. 8-Bit ALU Game Boy CPU Manual 9. INC n Description: Increment register n. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Set if carry from bit 3. C - Not affected. Opcodes: Instruction Parameters...
  • Page 89 Game Boy CPU Manual 3.3.3. 8-Bit ALU 10. DEC n Description: Decrement register n. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if reselt is zero. N - Set. H - Set if no borrow from bit 4. C - Not affected.

  • Page 90: 16-Bit Arithmetic

    3.3.4. 16-Bit Arithmetic Game Boy CPU Manual 3.3.4. 16-Bit Arithmetic 1. ADD HL,n Description: Add n to HL. Use with: n = BC,DE,HL,SP Flags affected: Z - Not affected. N - Reset. H - Set if carry from bit 11. C - Set if carry from bit 15.
  • Page 91 Game Boy CPU Manual 3.3.4. 16-Bit Arithmetic 2. ADD SP,n Description: Add n to Stack Pointer (SP). Use with: n = one byte signed immediate value (#). Flags affected: Z - Reset. N - Reset. H - Set or reset according to operation. C - Set or reset according to operation.
  • Page 92 3.3.4. 16-Bit Arithmetic Game Boy CPU Manual 3. INC nn Description: Increment register nn. Use with: nn = BC,DE,HL,SP Flags affected: None. Opcodes: Instruction Parameters Opcode Cycles Page 92 V 1.01...
  • Page 93 Game Boy CPU Manual 3.3.4. 16-Bit Arithmetic 4. DEC nn Description: Decrement register nn. Use with: nn = BC,DE,HL,SP Flags affected: None. Opcodes: Instruction Parameters Opcode Cycles by DP Page 93...

  • Page 94: Miscellaneous

    3.3.5. Miscellaneous Game Boy CPU Manual 3.3.5. Miscellaneous 1. SWAP n Description: Swap upper & lower nibles of n. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Reset. Opcodes: Instruction Parameters...
  • Page 95 Game Boy CPU Manual 3.3.5. Miscellaneous 2. DAA Description: Decimal adjust register A. This instruction adjusts register A so that the correct representation of Binary Coded Decimal (BCD) is obtained. Flags affected: Z - Set if register A is zero. N - Not affected.
  • Page 96 3.3.5. Miscellaneous Game Boy CPU Manual 4. CCF Description: Complement carry flag. If C flag is set, then reset it. If C flag is reset, then set it. Flags affected: Z - Not affected. N - Reset. H - Reset. C - Complemented.
  • Page 97 Game Boy CPU Manual 3.3.5. Miscellaneous 6. NOP Description: No operation. Opcodes: Instruction Parameters Opcode Cycles 7. HALT Description: Power down CPU until an interrupt occurs. Use this when ever possible to reduce energy consumption. Opcodes: Instruction Parameters Opcode Cycles HALT 8.
  • Page 98 3.3.5. Miscellaneous Game Boy CPU Manual 9. DI Description: This instruction disables interrupts but not immediately. Interrupts are disabled after instruction after DI is executed. Flags affected: None. Opcodes: Instruction Parameters Opcode Cycles 10. EI Description: Enable interrupts. This intruction enables interrupts but not immediately.

  • Page 99: Rotates & Shifts

    Game Boy CPU Manual 3.3.6. Rotates & Shifts 3.3.6. Rotates & Shifts 1. RLCA Description: Rotate A left. Old bit 7 to Carry flag. Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 7 data. Opcodes: Instruction Parameters...
  • Page 100 3.3.6. Rotates & Shifts Game Boy CPU Manual 3. RRCA Description: Rotate A right. Old bit 0 to Carry flag. Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 0 data. Opcodes: Instruction Parameters...
  • Page 101 Game Boy CPU Manual 3.3.6. Rotates & Shifts 5. RLC n Description: Rotate n left. Old bit 7 to Carry flag. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 7 data.
  • Page 102 3.3.6. Rotates & Shifts Game Boy CPU Manual 6. RL n Description: Rotate n left through Carry flag. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 7 data. Opcodes: Instruction Parameters...
  • Page 103 Game Boy CPU Manual 3.3.6. Rotates & Shifts 7. RRC n Description: Rotate n right. Old bit 0 to Carry flag. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 0 data.
  • Page 104 3.3.6. Rotates & Shifts Game Boy CPU Manual 8. RR n Description: Rotate n right through Carry flag. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 0 data. Opcodes: Instruction Parameters...
  • Page 105 Game Boy CPU Manual 3.3.6. Rotates & Shifts 9. SLA n Description: Shift n left into Carry. LSB of n set to 0. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset.
  • Page 106 3.3.6. Rotates & Shifts Game Boy CPU Manual 10. SRA n Description: Shift n right into Carry. MSB doesn't change. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 0 data.
  • Page 107 Game Boy CPU Manual 3.3.6. Rotates & Shifts 11. SRL n Description: Shift n right into Carry. MSB set to 0. Use with: n = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if result is zero. N - Reset. H - Reset. C - Contains old bit 0 data.

  • Page 108: Bit Opcodes

    3.3.7. Bit Opcodes Game Boy CPU Manual 3.3.7. Bit Opcodes 1. BIT b,r Description: Test bit b in register r. Use with: b = 0 - 7, r = A,B,C,D,E,H,L,(HL) Flags affected: Z - Set if bit b of register r is 0. N - Reset.
  • Page 109 Game Boy CPU Manual 3.3.7. Bit Opcodes 2. SET b,r Description: Set bit b in register r. Use with: b = 0 - 7, r = A,B,C,D,E,H,L,(HL) Flags affected: None. Opcodes: Instruction Parameters Opcode Cycles CB C7 CB C0 CB C1 CB C2 CB C3 CB C4...
  • Page 110 3.3.7. Bit Opcodes Game Boy CPU Manual 3. RES b,r Description: Reset bit b in register r. Use with: b = 0 - 7, r = A,B,C,D,E,H,L,(HL) Flags affected: None. Opcodes: Instruction Parameters Opcode Cycles CB 87 CB 80 CB 81 CB 82 CB 83 CB 84...

  • Page 111: Jumps

    Game Boy CPU Manual 3.3.8. Jumps 3.3.8. Jumps 1. JP nn Description: Jump to address nn. Use with: nn = two byte immediate value. (LS byte first.) Opcodes: Instruction Parameters Opcode Cycles 2. JP cc,nn Description: Jump to address n if following condition is true: cc = NZ, Jump if Z flag is reset.
  • Page 112 3.3.8. Jumps Game Boy CPU Manual 3. JP (HL) Description: Jump to address contained in HL. Opcodes: Instruction Parameters Opcode Cycles (HL) 4. JR n Description: Add n to current address and jump to it. Use with: n = one byte signed immediate value Opcodes: Instruction Parameters...
  • Page 113 Game Boy CPU Manual 3.3.8. Jumps 5. JR cc,n Description: If following condition is true then add n to current address and jump to it: Use with: n = one byte signed immediate value cc = NZ, Jump if Z flag is reset. cc = Z, Jump if Z flag is set.

  • Page 114: Calls

    3.3.9. Calls Game Boy CPU Manual 3.3.9. Calls 1. CALL nn Description: Push address of next instruction onto stack and then jump to address nn. Use with: nn = two byte immediate value. (LS byte first.) Opcodes: Instruction Parameters Opcode Cycles CALL Page 114...
  • Page 115 Game Boy CPU Manual 3.3.9. Calls 2. CALL cc,nn Description: Call address n if following condition is true: cc = NZ, Call if Z flag is reset. cc = Z, Call if Z flag is set. cc = NC, Call if C flag is reset. cc = C, Call if C flag is set.

  • Page 116: Restarts

    3.3.10. Restarts Game Boy CPU Manual 3.3.10. Restarts 1. RST n Description: Push present address onto stack. Jump to address $0000 + n. Use with: n = $00,$08,$10,$18,$20,$28,$30,$38 Opcodes: Instruction Parameters Opcode Cycles Page 116 V 1.01...

  • Page 117: Returns

    Game Boy CPU Manual 3.3.11. Returns 3.3.11. Returns 1. RET Description: Pop two bytes from stack & jump to that address. Opcodes: Instruction Parameters Opcode Cycles 2. RET cc Description: Return if following condition is true: Use with: cc = NZ, Return if Z flag is reset. cc = Z, Return if Z flag is set.
  • Page 118 3.3.11. Returns Game Boy CPU Manual 3. RETI Description: Pop two bytes from stack & jump to that address then enable interrupts. Opcodes: Instruction Parameters Opcode Cycles RETI Page 118 V 1.01...

  • Page 119: Super Game Boy Commands

    Game Boy CPU Manual 4. Super Game Boy commands 4. Super Game Boy commands 4.1. Foreword Super GameBoy Commands, Extracted by kOOPa, 15-Feb-98 ----------------------------------------------------- Last updated by: Bowser, 13-June-98 Updates: Block Area mode ($04) control codes updated Line mode ($05) written Divide mode ($06) written 1CHR mode ($07) written A SGB command transfer is 128 bits + a zero bit.

  • Page 120: Sgb Border

    4.2. Palettes Game Boy CPU Manual the SGB border palette. The SGB border palette is setup using command $14. There are 64 colors in this palette. The SGB color palettes may be set directly using commands $00-$03. There are a total of four of these palettes and they determine which colors are used in the main game action window.

  • Page 121: Main Action Window

    Game Boy CPU Manual 4.4. Main Action Window 4.4. Main Action Window The SGB cartridge that plugs into the SNES contains a GB CPU. The SNES is able to video capture the video output of this GB CPU and display it on the screen as the main game action window.

  • Page 122: Commands

    4.5. Commands Game Boy CPU Manual 4.5. Commands 1. Set SGB color Palettes 0 & 1 ($00,data) - Download color palettes 0 & 1 2 & 3 ($01,data) - Download color palettes 2 & 3 0 & 3 ($02,data) - Download color palettes 0 & 3 1 &...
  • Page 123 Game Boy CPU Manual 4.5. Commands Black or White with the Window Mask command before using the following four commands. If you want to freeze the screen, send palette data with the Attribute File ATF0-ATF44. In the event you are changing the screen by sending attribute data and color data at the same time, use Set SGB Palette Indirect command.
  • Page 124 4.5. Commands Game Boy CPU Manual $03 - %//xxyyzz Color Palette Designation xx = color palette outside surrounded area yy = color palette on surrounding block line zz = color palette inside surrounded area $04 - %///xxxxx xxxxx = start point H $05 - %///xxxxx xxxxx = start point V $06 - %///xxxxx...
  • Page 125 Game Boy CPU Manual 4.5. Commands 4. "Divide" Area Designation Mode ($06) $00 - %00101001 (number of packets must be 1) $01 - %/vxxyyzz control code = Mode (0 = divide horizontally, 1 = Divide vertical) = Colour palette ON division line = Colour palette ABOVE &...
  • Page 126 4.5. Commands Game Boy CPU Manual Writing style ( 0 = Left -> right, 1 = up -> down) $06 - %vvxxyyzz data vv = pal for dataset 1 xx = pal for dataset 2 yy = pal for dataset 3 zz = pal for dataset 4 $07 - %vvxxyyzz data etc...
  • Page 127 Game Boy CPU Manual 4.5. Commands 8. Set System Color Palette Data ($0b) 9. Enable/Disable Attraction Mode ($0c) 10. Speed Function ($0d) 11. SGB Function ($0e) 12. Super NES WRAM Transfer 1 ($0f) 13. Super NES WRAM Transfer 2 ($10) 14.
  • Page 128 4.5. Commands Game Boy CPU Manual info uses the same technique for determining extended colors. This tells the SNES which color palette to use to display each pixel. This allows a total of 16 colors per tile. Since SGB borders support up to 64 colors, access to the other colors are achieved by changing the Major palette number in the picture transfer tile map.
  • Page 129 Game Boy CPU Manual 4.5. Commands 18. Picture Transfer ($14) - Download border to SNES. The border (or tile map) that is downloaded is 32x28 tiles or 256x224 pixels. The regular GB screen fits right in the middle like this: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX...
  • Page 130 4.5. Commands Game Boy CPU Manual The tile map consists of a tile number byte & a tile attribute byte at each position on the map. A total of 32 lines are downloaded even though the last 4 lines are not visible. This would equal 64 bytes per line and a total of 2048 bytes per map.
  • Page 131 Game Boy CPU Manual 4.5. Commands 19. Set Attribute from ATF ($15) The data for 45 Attribute files is transfered with this command. Each ATtribute File is 90 bytes so 90x45 or 4050 bytes of data are transfered. Each attribute file uses 5 bytes per 8x8 horizontal line (20 x 4 char/byte x 2 bits/palette) to describe the color palettes of a line.
  • Page 132 22. Super NES OBJ Mode ($18) 23. SNES Color Palette Info The Nintendo Super Famicom is capable of displaying 256 colors from a palette of 32,768. These 256 colors are split into 16 palettes of 16 colors each. Only 8 of these palettes are accessible by the SGB.
  • Page 133 Game Boy CPU Manual 4.5. Commands 24. SGB Palette Selection There is actually only one color palette in the SNES but it is divided up into several sections for different SGB functions. These sections are referred to as Major (M) sections 0-7. Some SGB functions even divided some of these sections into sections.

  • Page 134: Appendix A

    It doesn't matter whether you program in C or assembly, this program will fix it. 3. The Nintendo scrolling graphic from $104 - $133 must be accurate. If one byte of it is changed then your programs will "lock up" after scrolling this graphic logo.
  • Page 135 Game Boy CPU Manual 5.1. Emulator Notes Write1: ldh a,[$41] ;read $ff41 and 2 jr nz,Write1 ld [hl],b ;turn on interrupts There should not be many instructions between the "jr nz" and write to memory "ld [hl],b". A worst case of 64 CPU clock cycles are available to access main video memory (not OAM!) following the "jr nz"...
  • Page 136 5.1. Emulator Notes Game Boy CPU Manual 6. If you are using sprites then you should not use the following commands when their register contents are in the range $fe00-$feff. inc bc inc de inc hl dec bc dec de dec hl If you don't follow this rule, sprite trash in the form of sprite "blink"...

  • Page 137: Typical Timing Diagram

    Game Boy CPU Manual 5.2. Typical timing diagram 5.2. Typical timing diagram (Based on an email from Philippe Pouliquen) The graphic shows a write followed by two reads (measured on a regular GameBoy): _________ _________ _________ CLK:____/ \_________/ \_________/ \_________/ _________________ /RD:_______/ \__________________________________________...
  • Page 138 5.2. Typical timing diagram Game Boy CPU Manual point at which /WR goes high after a write. f: 960ns point at which CLK goes high. This is also the point at which /CS goes high and the GameBoy stops driving the data bus. g: 990ns point at which /RD goes low for a read (30ns after CLK goes high).
  • Page 139 C O M M A N D I N D E X Game Boy CPU Manual Command Page Command Page Command Page ADC A,n LD (HL-),A ADD A,n LD (HLD),A RET cc ADD HL,n LD (HLI),A RETI ADD SP,n LD (nn),SP AND n LD A,(C) RLCA...

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