Nintendo GAME BOY Programming Manual page 25

The interrupt request flag (IF: 4) is set by negative edge input at one of the P13-
P10 terminals. Negative edge input requires a LOW period of 2
oscillation (DMG = 4 MHz, CGB = 4 MHz/8 MHz).
The interrupt request flag (IF: 4) also is set when a reset signal is input to the
/RESET terminal with a P13~P10 terminal in the LOW state.
2.4.2 Divider Registers
Name Address
DIV FF04
The upper 8 bits of the 16-bit counter that counts the basic clock frequency (f) can be referenced.
If an LD instruction is executed, these bits are cleared to 0 regardless of the value being written. f
= (4.194304 MHz).
Name
TIMA
2.4.3 Timer Registers
The main timer unit. Generates an interrupt when it overflows.
Name Address
TMA FF06
The value of TMA is loaded when TIMA overflows.
Name Address
TAC FF07
Bit 7 6 5 4
Address Bit 7 6 5
FF05
Bit 7 6 5 4 3
Bit 7 6 5 4 3
3 2 1 0
R/W Divider Read/Reset
4 3 2 1 0
2 1 0
R/W
2 1 0
R/W Timer Controller
Input Clock Select
00: f/2
01: f/2
10: f/2
11: f/2
Timer Stop
0: Stop Timer
1: Start Timer
25
Chapter 1: System
4
times source
9
f/2 (8192 Hz)
10
f/2 (4096 Hz)
11
f/2 (2048 Hz)
12
f/2 (1024 Hz)
13
f/2 (512 Hz)
14
f/2 (256 Hz)
15
f/2 (128 Hz)
16
f/2 (64 Hz)
R/W Timer Counter
Timer Modulo
10
(4.096 KHz)
4
(262.144 KHz)
6
(65.536 KHz)
8
(16.384 KHz)