Programming Items To Note - Nintendo GAME BOY Programming Manual

Game Boy Programming Manual
! One bank from among RAM banks 0-3 and the clock counter registers (RAM banks 08h-0Ch)
can be assigned to the external expansion working RAM area (A000h-BFFFh) of the CPU
memory space.
Bank 0Ch
Days(H)counter
Bank 0Bh
Days(L)counter
Hours counter Bank 0Ah
Minutes counter Bank 09h
Seconds
Bank 08h
Counter
: :
: :
RAM Address
: :
7FFFh
Bank 03h
6000h
Bank 02h
4000h
Bank 01h
2000h
Bank 00h
0000
3.5 Programming Cautions
3.5.1 Accessing the Clock Counters
Although counting up of the clock counters themselves and accessing the clock counters from the
CPU are performed asynchronously, clock counter failure may result if both operations are
performed at the same time. To prevent this, MBC3 provides an interface circuit for WR signals
from the CPU. Use of this circuit necessitates a delay when accessing control register 3 and the
clock counter registers (RTC_S, RTC_M, RTC_H, RTC_DL, and RTC_DH). Thus, whenever
accessing these registers consecutively, interpose a delay of 4 cycles between accesses.
When reading clock counter data:
•
Latch all clock counter data using control register 3.
•
Read the data in the clock counter registers.
CPU Address
DFFFh
Internal
Working
RAM
C000h
External
Expansion
Working
RAM
A000h
Display
RAM
8000h
Program
Switching
Area
4000h
Program
Residence
Area
0000
4-cycle delay required
222
ROM Address
1FFFFFh
Bank 7Fh
1FC000h
: :
0FFFFFh
Bank 3Fh
0FC000h
: :
07FFFFh
Bank IFh
07C000h
: :
0BFFFh
Bank 02h
08000h
Bank 01h
04000h
Bank 00h
00000