Branch Instructions Without A Delay Slot - Fujitsu MB91150 Series Hardware Manual

CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
3.7.2

Branch Instructions without a Delay Slot

During operation without a delay slot, the instructions are executed in the order of the
instruction list.
I Branch instructions without a delay slot
The following branch instructions without a delay slot are supported:
JMP @Ri
BRA label9
BC label9
BV label9
BLE label9
I Explanation of operation for branch instructions without a delay slot
During operation without a delay slot, the instructions are executed in the order of the instruction
list. The succeeding instruction is not executed before a branch.
[Example]
; Instruction list
...
LABEL
The execution cycle count of an instruction without a delay slot is two cycles for an instruction
with a branch and one cycle for an instruction without a branch. This increases the instruction
code efficiency as compared with branch instructions with a delay slot for which NOP was
specified because an appropriate instruction could not be entered in the delay slot. When an
effective instruction can be placed in the delay slot, the operation with a delay slot is selected. If
not, the operation without a delay slot is selected. This enables improvements with respect to
both execution speed and code efficiency.
52
CALL label12
BNO label9
BNC label9
BNV label9
BGT label9
ADD R1, R2 ;
BRA LABEL ; Branch instruction (without a delay slot)
MOV 2, R3 ; Not executed
ST R3, @R4 ; Branch destination
CALL @Ri RET
BEQ label9 BNE
BN label9 BP
BLT label9 BGE
BLS label9 BHI
label9
label9
label9
label9