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CHAPTER 4 BUS INTERFACE
4.5.5
Mixed Read/Write Cycles
This section describes the operations of the read/write cycle.
I Timing chart for mixed read/write cycles
Figure 4.5-13 "Sample timing chart for mixed read/write cycles 1" shows examples of read/write
cycle timing under the following conditions:
•
CS0 area
•
Bus width: 16 bits
•
Access type: reading in units of words
•
CS1 area
•
Bus width: 8 bits
•
Access format: Writing in units of half words
Note:
This model does not use CS4 and CS5 outputs.
❍ CS0 area: 16-bit bus, word read
Figure 4.5-13 Sample timing chart for mixed read/write cycles 1
CLK
A23-00
D31-24
D23-16
RD
WR0
WR1
(CS0)
(CS1)
[Operation]
•
In the above example, an idle cycle (in which no bus cycle is provided) is inserted when a
chip select area is switched. If an idle cycle is inserted between bus cycles, the address of
the preceding bus cycle is kept as output until the next bus cycle starts. Accordingly, the CS0
to CS5 corresponding to the output address are kept asserted.
•
In the above example, the 16-bit bus and 8-bit bus are mixed. Because the maximum bus
width is 16 bits, D23 to D16 and WR1 cannot be used as I/O ports even for an 8-bit access
area (CS1 area). The output of D23 to D16 is undefined and WR1 is negated.
140
BA1
BA2
BA1
BA2
#0
#2
#0
#2
#1
#3
Word read cycle
BA2
BA1
Idle
#0
#0
X
Halfword write cycle
CS0 area
CS1 area
BA1
BA
Idle
#1
#1
X
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