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2.2
Memory Space
2
The F
MC-16LX CPU has a 16M bytes memory space, to which all input to and output
2
from the F
MC-16LX CPU controlled data program is allocated. CPU has a 24-bit
address bus to access each resource.
■
Memory map
Figure 2.2-1 shows the F
Figure 2.2-1 Example showing correspondence between F
2
F
MC-16LX
CPU
[Device]
■
Address generation type
2
The F
MC-16LX CPU has two types of address generation. One is linear addressing that specifies
all 24-bit addresses with instructions. The other is bank addressing that specifies upper 8-bit
addresses with appropriate bank registers and lower 16-bit addresses with instructions.
Linear addressing has two types: one uses operands to directly specify 24-bit addresses; the
other refers to contents of the lower 24 bits in a 32-bit general-purpose register as addresses.
❍ Linear addressing (specified with 24-bit operand)
Figure 2.2-2 shows an example of linear addressing scheme specified with 24-bit operands.
Figure 2.2-2 Linear addressing (specified with 24-bit operand)
JMPP 123456H
Previous program
counter
New program counter
2
MC-16LX system and the associated memory map.
Program
Data
Interrupt
Peripheral
circuit
General-
purpose port
17
452D
12
3456
2
MC-16LX system and memory map
FFFFFF
H
Program area
FF8000
H
810000
H
Data area
800000
H
0000C0
H
Interrupt controller
0000B0
H
Peripheral circuit
000020
H
General-purpose port
000000
H
17452D
H
JMPP 123456
Next instruction
123456
H
CHAPTER 2 CPU
H
25
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