Appendix A: Drp Address Map Of The Gtm Transceiver In Ultrascale+ Fgpas; Gtm_Dual Primitive Drp Address Map - Xilinx Virtex UltraScale+ FPGAs User Manual

DRP Address Map of the GTM
Transceiver in UltraScale+ FGPAs

GTM_DUAL Primitive DRP Address Map

The following table lists the DRP map of the GTM_DUAL primitive sorted by address.
:
Note DO NOT modify the reserved bits. Attributes are not described explicitly and are set automatically
by the UltraScale FGPAs Transceiver Wizard. These attributes must be left at their defaults, except for use
cases that explicitly request different values.
Table 75: DRP Map of GTM_DUAL Primitive
DRP
DRP
Addres
Bits
s
0x001 [15:0]
0x002 [15:0]
0x003 [15:0]
0x004 [15:0]
0x005 [15:0]
0x006 [15:0]
0x007 [15:0]
0x008 [15:0]
0x009 [15:0]
0x00a [15:0]
0x00b [15:0]
0x00c [15:0]
0x00d [15:0]
0x00e [15:0]
0x00f [15:0]
0x010 [15:0]
0x011 [15:0]
0x012 [15:0]
0x013 [15:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
R/W Attribute Name
R/W CH0_TX_DRV_CFG0
R/W CH0_TX_DRV_CFG1
R/W CH0_TX_DRV_CFG2
R/W CH0_TX_ANA_CFG1
R/W CH0_TX_ANA_CFG2
R/W CH0_TX_ANA_CFG3
R/W CH0_TX_DRV_CFG3
R/W CH0_TX_DRV_CFG4
R/W CH0_TX_DRV_CFG5
R/W CH0_TX_LPBK_CFG0
R/W CH0_TX_LPBK_CFG1
R/W CH0_TX_ANA_CFG4
R/W CH0_TX_CAL_CFG0
R/W CH0_TX_CAL_CFG1
R/W CH0_TX_ANA_CFG0
R/W CH0_RX_ANA_CFG0
R/W CH0_RX_ANA_CFG1
R/W CH0_RX_PAD_CFG0
R/W CH0_RX_PAD_CFG1
Appendix A
Attribute
Attribute Bits
Encoding
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
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DRP
Encoding
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
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