Ac Coupled Reference Clock - Xilinx Virtex UltraScale+ FPGAs User Manual

Interfacing an LVPECL Oscillator to the GTM Transceiver Reference Clock
Figure 54:
LVPECL Oscillator
Notes relevant to the figure:
1. The resistor values are nominal. Refer to the oscillator data sheet for actual bias resistor
requirement.
2. Before completion of device configuration, the termination resistor is not calibrated and the
voltage level input to the clock input buffer should be made sure to not exceed the absolute
maximum rating as described in the UltraScale+ device data sheets (see
www.xilinx.com/documentation).

AC Coupled Reference Clock

AC coupling of the oscillator reference clock output to the GTM transceiver Dual reference clock
inputs serves multiple purposes:
• Blocking a DC current between the oscillator and the GTM transceiver Dual dedicated clock
input pins (which reduces the power consumption of both parts as well).
• Common mode voltage independence.
• The AC coupling capacitor forms a high-pass filter with the on-chip termination that
attenuates wander of the reference clock.
To minimize noise and power consumption, external AC coupling capacitors between the
sourcing oscillator and the GTM transceiver Dual dedicated reference clock input pins are
required.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Input
0.01 µF
240Ω
240Ω
0.01 µF
Chapter 5: Board Design Guidelines
Internal to
UltraScale+ Device
GTM Transceiver
Reference Clock
Input Buffer
X20935-053118
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