Rx Equalizer - Xilinx Virtex UltraScale+ FPGAs User Manual

Use Mode External AC Coupling
1
Board
~100 nF
~100 nF

RX Equalizer

A serial link bit error rate (BER) performance is a function of the transmitter, transmission media,
and receiver. The transmission media of the channel is bandwidth-limited, and the signal traveling
through is subjected to attenuation and distortion.
The GTM receiver is an ADC-based buffer that breaks the equalizer into two domains: analog
and digital. The incoming signal first passes through the analog stage consisting of a CTLE and
AGC stage. The signal is then digitized by the ADC, and passes through the Feed-Forward
Equalizer (FFE) and Decision-Feedback-Equalizer (DFE), as shown in the following figure.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Term
Voltage
(mV)
On 800
Figure 38:
UltraScale+ Device
ACJTAG RX
MGTAVTT
50Ω
PAD_RTERM_VCOM_MODE = 2'b11
50Ω
MGTAVTT
ACJTAG RX
Suggested Protocols and Usage Notes
Attribute settings:
PAD_RTERM_VCOM_MODE = 2'b11
PAD_RTERM_VCOM_LVL = 4'b1010
Use Mode 1
PAD_RTERM_VCOM_LVL = 4'b1010
+
Programmable
–
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Chapter 4: Receiver
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