Rx Fabric Clock Output Control - Xilinx Virtex UltraScale+ FPGAs User Manual

Table 52: CDR Ports (cont'd)
Port
CH[0/1]_RXCDRFRRESET
CH[0/1]_RXCDRHOLD
CH[0/1]_RXCDRINCPCTRL
CH[0/1]_RXCDRPHRESET
CH[0/1]_RXCDRFREQOS
The following table defines the CDR attributes.
Table 53: CDR Attributes
Attribute
CH[0/1]_RX_CDR_CFG0A
CH[0/1]_RX_CDR_CFG0B
CH[0/1]_RX_CDR_CFG1A
CH[0/1]_RX_CDR_CFG1B
CH[0/1]_RX_CDR_CFG2A
CH[0/1]_RX_CDR_CFG2B
CH[0/1]_RX_CDR_CFG3A
CH[0/1]_RX_CDR_CFG3B
CH[0/1]_RX_CDR_CFG4A
CH[0/1]_RX_CDR_CFG4B

RX Fabric Clock Output Control

The RX Clock Divider Control block has two main components: serial clock divider control, and
parallel clock divider and selector control. The clock divider and selector details are illustrated in
the following figure.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Async
In Async
In Async
In Async
In Async
Type
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
16-bit CDR configuration. Use the recommended value
from the Wizard.
Chapter 4: Receiver
Description
Reserved. Use the recommended value
from the Wizard.
Hold the CDR control loop frozen.
Reserved. Use the recommended value
from the Wizard.
Reserved. Use the recommended value
from the Wizard.
Reserved. Use the recommended value
from the Wizard.
Description
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