Cfgctrl Register - Texas Instruments CC3200 Technical Reference Manual

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3.3.1.16 CFGCTRL Register (offset = D14h) [reset = 200h]
CFGCTRL is shown in
NOTE: his register can only be accessed from privileged mode. The CFGCTRL register controls entry to
Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK
register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the
SWTRIG register by unprivileged software.
31 30
23 22
15 14
7 6
RESERVED
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit Field
31-10 RESERVED
9 STKALIGN
8 BFHFMIGN
7-5 RESERVED
4 DIV0
3 UNALIGNED
SWRU367D – June 2014 – Revised May 2018
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Figure 3-16 and described in
Figure 3-16. CFGCTRL Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
DIV0
R/W-0h
Table 3-19. CFGCTRL Register Field Descriptions
Type Reset
R 0h
R/W 1h
R/W 0h
R 0h
R/W 0h
R/W 0h
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Table 3-19.
27 26
19 18
11 10
3 2
UNALIGNED RESERVED
R/W-0h R-0h
Description
Stack Alignment on Exception Entry On exception entry, the
processor uses bit 9 of the stacked PSR to indicate the stack
alignment.
On return from the exception, it uses this stacked bit to restore the
correct stack alignment.
0h = The stack is 4-byte aligned.
1h = The stack is 8-byte aligned.
Ignore Bus Fault in NMI and Fault This bit enables handlers with
priority -1 or -2 to ignore data bus faults caused by load and store
instructions.
The setting of this bit applies to the hard fault, NMI, and
FAULTMASK escalated handlers.
Set this bit only when the handler and its data are in absolutely safe
memory.
The normal use of this bit is to probe system devices and bridges to
detect control path problems and fix them.
0h = Data bus faults caused by load and store instructions cause a
lock-up.
1h = Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
Trap on Divide by 0 This bit enables faulting or halting when the
processor executes an SDIV or UDIV instruction with a divisor of 0.
0h = Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
1h = Trap on divide by 0.
Trap on Unaligned Access Unaligned LDM, STM, LDRD, and STRD
instructions always fault regardless of whether UNALIGNED is set.
0h = Do not trap on unaligned halfword and word accesses.
1h = Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
Register Map
25 24
17 16
9 8
STKALIGN BFHFMIGN
R/W-1h R/W-0h
1 0
MANIPEND BASETHR
R/W-0h R/W-0h
83
Cortex-M4 Peripherals