5.5.5 CDCE62005 default value on the EVM
The below tables show the default configurations inside the static RAM of CDCE62005 and
CDCE62002. The FPGA programs and completes the configurations on CDCE62005 and
CDCE62002 before RESETz de‐asserted.
Table 5.2: CLK2, CDCE62005 Register configurations
Table 5.3: CLK3, CDCE62005 Register configurations
Register NO.
Programming value
Register 0
E984_0320(H)
Register 1
6984_0301(H)
Register 2
E902_0302(H)
Register 3
E984_0303(H)
Register 4
6986_0314(H)
Register 5
101C_0BE5(H)
Register 6
04BE_0F06(H)
Register 7
FD00_37F7(H)
Register NO.
Programming value
Register 0
E940_0020(H)
Register 1
E980_0301(H)
Register 2
E980_0302(H)
Register 3
E940_0003(H)
Register 4
6986_0314(H)
Register 5
107C_0BF5(H)
Register 6
84BE_19A6(H)
Register 7
FD00_37F7(H)
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