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Texas Instruments TM4C1294NCPDT ARM Manuals
Manuals and User Guides for Texas Instruments TM4C1294NCPDT ARM. We have
1
Texas Instruments TM4C1294NCPDT ARM manual available for free PDF download: Datasheet
Texas Instruments TM4C1294NCPDT Datasheet (1890 pages)
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 10.11 MB
Table of Contents
Table of Contents
3
Table of Contents
19
Table of Contents
25
Table of Contents
42
Revision History
45
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About this Document
48
Audience
48
About this Manual
48
Related Documents
48
Documentation Conventions
49
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Architectural Overview
51
Tiva™ C Series Overview
51
TM4C1294NCPDT Microcontroller Overview
52
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Figure 1-1. Tiva TM4C1294NCPDT Microcontroller High-Level Block Diagram
54
ARM Cortex-M4F Processor Core
55
TM4C1294NCPDT Microcontroller Features
55
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On-Chip Memory
57
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External Peripheral Interface
59
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Cyclical Redundancy Check (CRC)
61
Serial Communications Peripherals
61
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System Integration
67
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Advanced Motion Control
74
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Analog
76
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JTAG and ARM Serial Wire Debug
78
Packaging and Temperature
78
TM4C1294NCPDT Microcontroller Hardware Details
78
Kits
79
Support Information
79
The Cortex-M4F Processor
80
Block Diagram
81
Integrated Configurable Debug
82
Overview
82
System-Level Interface
82
Cortex-M4F System Component Details
83
Trace Port Interface Unit (TPIU)
83
Processor Mode and Privilege Levels for Software Execution
84
Programming Model
84
Register Map
85
Stacks
85
Figure 2-3. Cortex-M4F Register Set
86
Register Descriptions
87
Register 1: Cortex General-Purpose Register 0 (R0)
88
Register 14: Stack Pointer (SP)
89
Register 15: Link Register (LR)
90
Register 16: Program Counter (PC)
91
Table 2-3. PSR Register Combinations
92
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Register 18: Priority Mask Register (PRIMASK)
96
Register 19: Fault Mask Register (FAULTMASK)
97
Register 20: Base Priority Mask Register (BASEPRI)
98
Register 21: Control Register (CONTROL)
99
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Register 22: Floating-Point Status Control (FPSC)
101
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Data Types
103
Exceptions and Interrupts
103
Memory Model
103
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Memory Regions, Types and Attributes
106
Behavior of Memory Accesses
107
Memory System Ordering of Memory Accesses
107
Software Ordering of Memory Accesses
108
Bit-Banding
109
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Data Storage
111
Synchronization Primitives
112
Exception Model
113
Exception States
114
Exception Types
114
Table 2-8. Exception Types
115
Table 2-9. Interrupts
116
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Exception Handlers
119
Vector Table
119
Exception Entry and Return
120
Exception Priorities
120
Interrupt Priority Grouping
120
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Figure 2-7. Exception Stack Frame
122
Fault Handling
123
Fault Escalation and Hard Faults
124
Fault Types
124
Fault Status Registers and Fault Address Registers
125
Lockup
125
Entering Sleep Modes
126
Power Management
126
Wake up from Sleep Mode
126
Instruction Set Summary
127
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Cortex-M4 Peripherals
134
Functional Description
134
System Timer (Systick)
135
Nested Vectored Interrupt Controller (NVIC)
136
Memory Protection Unit (MPU)
137
System Control Block (SCB)
137
Table 3-2. Memory Attributes Summary
138
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Figure 3-1. SRD Use Example
140
Table 3-4. Cache Policy for Memory Attribute Encoding
141
Floating-Point Unit (FPU)
142
Figure 3-2. FPU Register Bank
143
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Table 3-7. Qnan and Snan Handling
145
Register Map
146
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System Timer (Systick) Register Descriptions
149
Register 1: Systick Control and Status Register (STCTRL), Offset 0X010
150
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Register 2: Systick Reload Value Register (STRELOAD), Offset 0X014
152
NVIC Register Descriptions
153
Register 4: Interrupt 0-31 Set Enable (EN0), Offset 0X100
154
Register 8: Interrupt 0-31 Clear Enable (DIS0), Offset 0X180
155
Register 12: Interrupt 0-31 Set Pending (PEND0), Offset 0X200
156
Register 16: Interrupt 0-31 Clear Pending (UNPEND0), Offset 0X280
157
Register 20: Interrupt 0-31 Active Bit (ACTIVE0), Offset 0X300
158
Register 24: Interrupt 0-3 Priority (PRI0), Offset 0X400
159
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Register 40: Interrupt 64-67 Priority (PRI16), Offset 0X440
161
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System Control Block (SCB) Register Descriptions
163
Register 54: Auxiliary Control (ACTLR), Offset 0X008
164
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Register 55: CPU ID Base (CPUID), Offset 0Xd00
166
Register 56: Interrupt Control and State (INTCTRL), Offset 0Xd04
167
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Register 57: Vector Table Offset (VTABLE), Offset 0Xd08
170
Table 3-9. Interrupt Priority Levels
171
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Register 59: System Control (SYSCTRL), Offset 0Xd10
173
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Register 60: Configuration and Control (CFGCTRL), Offset 0Xd14
175
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Register 61: System Handler Priority 1 (SYSPRI1), Offset 0Xd18
177
Register 62: System Handler Priority 2 (SYSPRI2), Offset 0Xd1C
178
Register 63: System Handler Priority 3 (SYSPRI3), Offset 0Xd20
179
Register 64: System Handler Control and State (SYSHNDCTRL), Offset 0Xd24
180
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Register 65: Configurable Fault Status (FAULTSTAT), Offset 0Xd28
184
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Register 66: Hard Fault Status (HFAULTSTAT), Offset 0Xd2C
190
Register 67: Memory Management Fault Address (MMADDR), Offset 0Xd34
191
Memory Protection Unit (MPU) Register Descriptions
192
Register 69: MPU Type (MPUTYPE), Offset 0Xd90
193
Register 70: MPU Control (MPUCTRL), Offset 0Xd94
194
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Register 71: MPU Region Number (MPUNUMBER), Offset 0Xd98
196
Register 72: MPU Region Base Address (MPUBASE), Offset 0Xd9C
197
Register 73: MPU Region Base Address Alias 1 (MPUBASE1), Offset 0Xda4
197
Register 74: MPU Region Base Address Alias 2 (MPUBASE2), Offset 0Xdac
197
Register 75: MPU Region Base Address Alias 3 (MPUBASE3), Offset 0Xdb4
197
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Register 76: MPU Region Attribute and Size (MPUATTR), Offset 0Xda0
199
Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), Offset 0Xda8
199
Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), Offset 0Xdb0
199
Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), Offset 0Xdb8
199
Table 3-10. Example SIZE Field Values
199
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Floating-Point Unit (FPU) Register Descriptions
201
Register 80: Coprocessor Access Control (CPAC), Offset 0Xd88
202
Register 81: Floating-Point Context Control (FPCC), Offset 0Xf34
203
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Register 82: Floating-Point Context Address (FPCA), Offset 0Xf38
205
Register 83: Floating-Point Default Status Control (FPDSC), Offset 0Xf3C
206
JTAG Interface
207
Block Diagram
208
Signal Description
208
Functional Description
209
JTAG Interface Pins
209
Table 4-2. JTAG Port Pins State after Power-On Reset or RST Assertion
210
JTAG TAP Controller
211
Operational Considerations
212
Shift Registers
212
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Initialization and Configuration
215
Register Descriptions
215
Instruction Register (IR)
216
Data Registers
217
Figure 4-3. IDCODE Register Format
218
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Device Identification
220
Functional Description
220
Signal Description
220
System Control
220
Reset Control
221
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Figure 5-1. Basic RST Configuration
224
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Non-Maskable Interrupt
228
Power Control
229
Clock Control
230
Table 5-3. Clock Source Options
231
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Figure 5-5. Main Clock Tree
233
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Table 5-5. System Clock Frequency
235
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Table 5-7. Actual PLL Frequency
238
System Control
239
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Figure 5-6. Module Clock Selection
242
Table 5-8. Peripheral Memory Power Control
243
Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
244
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Initialization and Configuration
246
Register Map
247
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System Control Register Descriptions (System Control Offset)
254
Register 1: Device Identification 0 (DID0), Offset 0X000
255
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Register 2: Device Identification 1 (DID1), Offset 0X004
257
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Register 3: Power-Temp Brown out Control (PTBOCTL), Offset 0X038
259
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Register 4: Raw Interrupt Status (RIS), Offset 0X050
261
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Register 5: Interrupt Mask Control (IMC), Offset 0X054
263
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Register 6: Masked Interrupt Status and Clear (MISC), Offset 0X058
265
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Register 7: Reset Cause (RESC), Offset 0X05C
267
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Register 8: Power-Temperature Cause (PWRTC), Offset 0X060
270
Register 9: NMI Cause Register (NMIC), Offset 0X064
271
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Register 10: Main Oscillator Control (MOSCCTL), Offset 0X07C
273
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Register 11: Run and Sleep Mode Configuration Register (RSCLKCFG), Offset 0X0B0
275
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Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0), Offset 0X0C0
277
Table 5-12. MEMTIM0 Register Configuration Versus Frequency
277
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Register 13: Alternate Clock Configuration (ALTCLKCFG), Offset 0X138
280
Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), Offset 0X144
281
Table 5-13. MOSC Configurations
281
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Register 15: Divisor and Source Clock Configuration (DIVSCLK), Offset 0X148
284
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Register 16: System Properties (SYSPROP), Offset 0X14C
286
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Register 17: Precision Internal Oscillator Calibration (PIOSCCAL), Offset 0X150
289
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Register 18: Precision Internal Oscillator Statistics (PIOSCSTAT), Offset 0X154
291
Register 19: PLL Frequency 0 (PLLFREQ0), Offset 0X160
292
Register 20: PLL Frequency 1 (PLLFREQ1), Offset 0X164
293
Register 21: PLL Status (PLLSTAT), Offset 0X168
294
Register 22: Sleep Power Configuration (SLPPWRCFG), Offset 0X188
295
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Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), Offset 0X18C
297
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Register 24: Non-Volatile Memory Information (NVMSTAT), Offset 0X1A0
299
Register 25: LDO Sleep Power Control (LDOSPCTL), Offset 0X1B4
300
Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
300
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Register 26: LDO Sleep Power Calibration (LDOSPCAL), Offset 0X1B8
302
Register 27: LDO Deep-Sleep Power Control (LDODPCTL), Offset 0X1Bc
303
Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
303
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Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), Offset 0X1C0
305
Register 29: Sleep / Deep-Sleep Power Mode Status (SDPMST), Offset 0X1Cc
306
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Register 30: Reset Behavior Control Register (RESBEHAVCTL), Offset 0X1D8
309
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Register 31: Hardware System Service Request (HSSR), Offset 0X1F4
311
Register 32: USB Power Domain Status (USBPDS), Offset 0X280
312
Register 33: USB Memory Power Control (USBMPC), Offset 0X284
313
Register 34: Ethernet MAC Power Domain Status (EMACPDS), Offset 0X288
314
Register 35: Ethernet MAC Memory Power Control (EMACMPC), Offset 0X28C
315
Register 36: CAN 0 Power Domain Status (CAN0PDS), Offset 0X298
316
Register 37: CAN 0 Memory Power Control (CAN0MPC), Offset 0X29C
317
Register 38: CAN 1 Power Domain Status (CAN1PDS), Offset 0X2A0
318
Register 39: CAN 1 Memory Power Control (CAN1MPC), Offset 0X2A4
319
Register 40: Watchdog Timer Peripheral Present (PPWD), Offset 0X300
320
Register 41: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), Offset 0X304
321
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Register 42: General-Purpose Input/Output Peripheral Present (PPGPIO), Offset 0X308
323
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Register 43: Micro Direct Memory Access Peripheral Present (PPDMA), Offset 0X30C
326
Register 44: EPI Peripheral Present (PPEPI), Offset 0X310
327
Register 45: Hibernation Peripheral Present (PPHIB), Offset 0X314
328
Register 46: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), Offset 0X318
329
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Register 47: Synchronous Serial Interface Peripheral Present (PPSSI), Offset 0X31C
331
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Register 48: Inter-Integrated Circuit Peripheral Present (PPI2C), Offset 0X320
333
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Register 49: Universal Serial Bus Peripheral Present (PPUSB), Offset 0X328
335
Register 50: Ethernet PHY Peripheral Present (PPEPHY), Offset 0X330
336
Register 51: Controller Area Network Peripheral Present (PPCAN), Offset 0X334
337
Register 52: Analog-To-Digital Converter Peripheral Present (PPADC), Offset 0X338
338
Register 53: Analog Comparator Peripheral Present (PPACMP), Offset 0X33C
339
Register 54: Pulse Width Modulator Peripheral Present (PPPWM), Offset 0X340
340
Register 55: Quadrature Encoder Interface Peripheral Present (PPQEI), Offset 0X344
341
Register 56: Low Pin Count Interface Peripheral Present (PPLPC), Offset 0X348
342
Register 57: Platform Environment Control Interface Peripheral Present (PPPECI), Offset 0X350
343
Register 58: Fan Control Peripheral Present (PPFAN), Offset 0X354
344
Register 59: EEPROM Peripheral Present (PPEEPROM), Offset 0X358
345
Register 60: 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), Offset 0X35C
346
Register 61: Remote Temperature Sensor Peripheral Present (PPRTS), Offset 0X370
347
Register 62: CRC Module Peripheral Present (PPCCM), Offset 0X374
348
Register 63: LCD Peripheral Present (PPLCD), Offset 0X390
349
Register 64: 1-Wire Peripheral Present (PPOWIRE), Offset 0X398
350
Register 65: Ethernet MAC Peripheral Present (PPEMAC), Offset 0X39C
351
Register 66: Power Regulator Bus Peripheral Present (PPPRB), Offset 0X3A0
352
Register 67: Human Interface Master Peripheral Present (PPHIM), Offset 0X3A4
353
Register 68: Watchdog Timer Software Reset (SRWD), Offset 0X500
354
Register 69: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), Offset 0X504
355
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Register 70: General-Purpose Input/Output Software Reset (SRGPIO), Offset 0X508
357
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Register 71: Micro Direct Memory Access Software Reset (SRDMA), Offset 0X50C
360
Register 72: EPI Software Reset (SREPI), Offset 0X510
361
Register 73: Hibernation Software Reset (SRHIB), Offset 0X514
362
Register 74: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), Offset 0X518
363
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Register 75: Synchronous Serial Interface Software Reset (SRSSI), Offset 0X51C
365
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Register 76: Inter-Integrated Circuit Software Reset (SRI2C), Offset 0X520
367
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Register 77: Universal Serial Bus Software Reset (SRUSB), Offset 0X528
369
Register 78: Ethernet PHY Software Reset (SREPHY), Offset 0X530
370
Register 79: Controller Area Network Software Reset (SRCAN), Offset 0X534
371
Register 80: Analog-To-Digital Converter Software Reset (SRADC), Offset 0X538
372
Register 81: Analog Comparator Software Reset (SRACMP), Offset 0X53C
373
Register 82: Pulse Width Modulator Software Reset (SRPWM), Offset 0X540
374
Register 83: Quadrature Encoder Interface Software Reset (SRQEI), Offset 0X544
375
Register 84: EEPROM Software Reset (SREEPROM), Offset 0X558
376
Register 85: CRC Module Software Reset (SRCCM), Offset 0X574
377
Register 86: Ethernet MAC Software Reset (SREMAC), Offset 0X59C
378
Register 87: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), Offset 0X600
379
Register 88: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), Offset 0X604
380
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Register 89: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), Offset 0X608
382
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384
Register 90: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), Offset 0X60C
385
Register 91: EPI Run Mode Clock Gating Control (RCGCEPI), Offset 0X610
386
Register 92: Hibernation Run Mode Clock Gating Control (RCGCHIB), Offset 0X614
387
Register 93: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART), Offset 0X618
388
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Register 94: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), Offset 0X61C
390
Register 95: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), Offset 0X620
391
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Register 96: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), Offset 0X628
393
Register 97: Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY), Offset 0X630
394
Register 98: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), Offset 0X634
395
Register 99: Analog-To-Digital Converter Run Mode Clock Gating Control (RCGCADC), Offset 0X638
396
Register 100: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), Offset 0X63C
397
Register 101: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), Offset 0X640
398
0X644
399
Register 103: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), Offset 0X658
400
Register 104: CRC Module Run Mode Clock Gating Control (RCGCCCM), Offset 0X674
401
Register 105: Ethernet MAC Run Mode Clock Gating Control (RCGCEMAC), Offset 0X69C
402
Register 106: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), Offset 0X700
403
Register 107: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), Offset 0X704
404
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0X708
406
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0X70C
409
Register 110: EPI Sleep Mode Clock Gating Control (SCGCEPI), Offset 0X710
410
Register 111: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), Offset 0X714
411
(SCGCUART), Offset 0X718
412
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0X71C
414
Register 114: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), Offset 0X720
415
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416
Register 115: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), Offset 0X728
417
Register 116: Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY), Offset 0X730
418
Register 117: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), Offset 0X734
419
0X738
420
Register 119: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), Offset 0X73C
421
Register 120: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), Offset 0X740
422
0X744
423
Register 122: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), Offset 0X758
424
Register 123: CRC Module Sleep Mode Clock Gating Control (SCGCCCM), Offset 0X774
425
Register 124: Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC), Offset 0X79C
426
Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), Offset 0X800
427
Offset 0X804
428
Register 126: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER Offset 0X804
428
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Register 127: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), Offset 0X808
430
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0X80C
433
Register 129: EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI), Offset 0X810
434
Register 130: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), Offset 0X814
435
(DCGCUART), Offset 0X818
436
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0X81C
438
0X820
439
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0X828
441
Register 135: Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY), Offset 0X830
442
0X834
443
0X838
444
0X83C
445
0X840
446
Register 140: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), Offset 0X844
447
Register 141: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), Offset 0X858
448
Register 142: CRC Module Deep-Sleep Mode Clock Gating Control (DCGCCCM), Offset 0X874
449
Register 143: Ethernet MAC Deep-Sleep Mode Clock Gating Control (DCGCEMAC), Offset 0X89C
450
Register 144: Watchdog Timer Power Control (PCWD), Offset 0X900
451
Table 5-16. Module Power Control
451
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Register 145: 16/32-Bit General-Purpose Timer Power Control (PCTIMER), Offset 0X904
453
Table 5-17. Module Power Control
453
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455
Register 146: General-Purpose Input/Output Power Control (PCGPIO), Offset 0X908
456
Table 5-18. Module Power Control
456
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Register 147: Micro Direct Memory Access Power Control (PCDMA), Offset 0X90C
461
Table 5-19. Module Power Control
461
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Register 148: External Peripheral Interface Power Control (PCEPI), Offset 0X910
463
Table 5-20. Module Power Control
463
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Register 149: Hibernation Power Control (PCHIB), Offset 0X914
465
Table 5-21. Module Power Control
465
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Register 150: Universal Asynchronous Receiver/Transmitter Power Control (PCUART), Offset 0X918
467
Table 5-22. Module Power Control
467
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Register 151: Synchronous Serial Interface Power Control (PCSSI), Offset 0X91C
470
Table 5-23. Module Power Control
470
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Register 152: Inter-Integrated Circuit Power Control (PCI2C), Offset 0X920
472
Table 5-24. Module Power Control
472
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Register 153: Universal Serial Bus Power Control (PCUSB), Offset 0X928
476
Table 5-25. Module Power Control
476
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Register 154: Ethernet PHY Power Control (PCEPHY), Offset 0X930
478
Table 5-26. Module Power Control
478
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Register 155: Controller Area Network Power Control (PCCAN), Offset 0X934
480
Table 5-27. Module Power Control
480
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Register 156: Analog-To-Digital Converter Power Control (PCADC), Offset 0X938
482
Table 5-28. Module Power Control
482
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Register 157: Analog Comparator Power Control (PCACMP), Offset 0X93C
484
Table 5-29. Module Power Control
484
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Register 158: Pulse Width Modulator Power Control (PCPWM), Offset 0X940
486
Table 5-30. Module Power Control
486
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Register 159: Quadrature Encoder Interface Power Control (PCQEI), Offset 0X944
488
Table 5-31. Module Power Control
488
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Register 160: EEPROM Power Control (PCEEPROM), Offset 0X958
490
Table 5-32. Module Power Control
490
Texas Instruments-Production Data
491
Register 161: CRC Module Power Control (PCCCM), Offset 0X974
492
Table 5-33. Module Power Control
492
Texas Instruments-Production Data
493
Register 162: Ethernet MAC Power Control (PCEMAC), Offset 0X99C
494
Table 5-34. Module Power Control
494
Texas Instruments-Production Data
495
Register 163: Watchdog Timer Peripheral Ready (PRWD), Offset 0Xa00
496
Register 164: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), Offset 0Xa04
497
Texas Instruments-Production Data
498
Register 165: General-Purpose Input/Output Peripheral Ready (PRGPIO), Offset 0Xa08
499
Texas Instruments-Production Data
500
Texas Instruments-Production Data
501
Register 166: Micro Direct Memory Access Peripheral Ready (PRDMA), Offset 0Xa0C
502
Register 167: EPI Peripheral Ready (PREPI), Offset 0Xa10
503
Register 168: Hibernation Peripheral Ready (PRHIB), Offset 0Xa14
504
Register 169: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), Offset
505
0Xa18
505
Texas Instruments-Production Data
506
Register 170: Synchronous Serial Interface Peripheral Ready (PRSSI), Offset 0Xa1C
507
Texas Instruments-Production Data
508
Register 171: Inter-Integrated Circuit Peripheral Ready (PRI2C), Offset 0Xa20
509
Texas Instruments-Production Data
510
Texas Instruments-Production Data
511
Register 172: Universal Serial Bus Peripheral Ready (PRUSB), Offset 0Xa28
512
Register 173: Ethernet PHY Peripheral Ready (PREPHY), Offset 0Xa30
513
Register 174: Controller Area Network Peripheral Ready (PRCAN), Offset 0Xa34
514
Register 175: Analog-To-Digital Converter Peripheral Ready (PRADC), Offset 0Xa38
515
Register 176: Analog Comparator Peripheral Ready (PRACMP), Offset 0Xa3C
516
Register 177: Pulse Width Modulator Peripheral Ready (PRPWM), Offset 0Xa40
517
Register 178: Quadrature Encoder Interface Peripheral Ready (PRQEI), Offset 0Xa44
518
Register 179: EEPROM Peripheral Ready (PREEPROM), Offset 0Xa58
519
Register 180: CRC Module Peripheral Ready (PRCCM), Offset 0Xa74
520
Register 181: Ethernet MAC Peripheral Ready (PREMAC), Offset 0Xa9C
521
Register 182: Unique ID 0 (UNIQUEID0), Offset 0Xf20
522
Register 183: Unique ID 1 (UNIQUEID1), Offset 0Xf24
522
Register 184: Unique ID 2 (UNIQUEID2), Offset 0Xf28
522
Register 185: Unique ID 3 (UNIQUEID3), Offset 0Xf2C
522
Processor Support and Exception Module
523
Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), Offset 0X000
524
Texas Instruments-Production Data
525
Register 2: System Exception Interrupt Mask (SYSEXCIM), Offset 0X004
526
Texas Instruments-Production Data
527
Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), Offset 0X008
528
Texas Instruments-Production Data
529
Register 4: System Exception Interrupt Clear (SYSEXCIC), Offset 0X00C
530
Hibernation Module
531
Texas Instruments-Production Data
532
Block Diagram
533
Functional Description
534
Register Access Timing
535
Texas Instruments-Production Data
536
Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source
537
System Implementation
538
Battery Management
539
Texas Instruments-Production Data
540
Texas Instruments-Production Data
541
Tamper
542
Figure 7-8. Tamper Pad with Glitch Filtering
543
Texas Instruments-Production Data
544
Battery-Backed Memory
545
Power Control Using VDD3ON Mode
546
Arbitrary Power Removal
547
Initialization and Configuration
548
RTC Match Functionality (no Hibernation)
549
External Wake-Up from Hibernation
550
RTC or External Wake-Up from Hibernation
551
Table 7-3. Hibernation Module Register Map
552
Register Descriptions
553
Register 1: Hibernation RTC Counter (HIBRTCC), Offset 0X000
554
Register 2: Hibernation RTC Match 0 (HIBRTCM0), Offset 0X004
555
Register 3: Hibernation RTC Load (HIBRTCLD), Offset 0X00C
556
Register 4: Hibernation Control (HIBCTL), Offset 0X010
557
Register 5: Hibernation Interrupt Mask (HIBIM), Offset 0X014
562
Register 6: Hibernation Raw Interrupt Status (HIBRIS), Offset 0X018
564
Register 7: Hibernation Masked Interrupt Status (HIBMIS), Offset 0X01C
566
Register 8: Hibernation Interrupt Clear (HIBIC), Offset 0X020
568
Register 9: Hibernation RTC Trim (HIBRTCT), Offset 0X024
570
Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), Offset 0X028
571
Register 11: Hibernation IO Configuration (HIBIO), Offset 0X02C
572
Register 12: Hibernation Data (HIBDATA), Offset 0X030-0X06F
574
Register 13: Hibernation Calendar Control (HIBCALCTL), Offset 0X300
575
Register 14: Hibernation Calendar 0 (HIBCAL0), Offset 0X310
576
Register 15: Hibernation Calendar 1 (HIBCAL1), Offset 0X314
578
Register 16: Hibernation Calendar Load 0 (HIBCALLD0), Offset 0X320
580
Register 17: Hibernation Calendar Load (HIBCALLD1), Offset 0X324
582
Register 18: Hibernation Calendar Match 0 (HIBCALM0), Offset 0X330
583
Register 19: Hibernation Calendar Match 1 (HIBCALM1), Offset 0X334
585
Register 20: Hibernation Lock (HIBLOCK), Offset 0X360
586
Register 21: HIB Tamper Control (HIBTPCTL), Offset 0X400
587
Register 22: HIB Tamper Status (HIBTPSTAT), Offset 0X404
589
Register 23: HIB Tamper I/O Control (HIBTPIO), Offset 0X410
591
Register 24: HIB Tamper Log 0 (HIBTPLOG0), Offset 0X4E0
595
Register 25: HIB Tamper Log 2 (HIBTPLOG2), Offset 0X4E8
595
Register 26: HIB Tamper Log 4 (HIBTPLOG4), Offset 0X4F0
595
Register 27: HIB Tamper Log 6 (HIBTPLOG6), Offset 0X4F8
595
Register 28: HIB Tamper Log 1 (HIBTPLOG1), Offset 0X4E4
596
Register 29: HIB Tamper Log 3 (HIBTPLOG3), Offset 0X4Ec
596
Register 30: HIB Tamper Log 5 (HIBTPLOG5), Offset 0X4F4
596
Register 31: HIB Tamper Log 7 (HIBTPLOG7), Offset 0X4Fc
596
Register 32: Hibernation Peripheral Properties (HIBPP) , Offset 0Xfc0
598
Register 33: Hibernation Clock Control (HIBCC), Offset 0Xfc8
599
Internal Memory
600
Figure 8-1. Internal Memory Block Diagram
601
Functional Description
602
Flash Memory
604
Figure 8-2. Flash Memory Configuration
605
Figure 8-3. Single 256-Bit Prefetch Buffer Set
606
Figure 8-5. Single Cycle Access, 0 Wait States
607
Figure 8-6. Prefetch Fills from Flash
608
Figure 8-7. Mirror Mode Function
609
Table 8-2. Flash Memory Protection Policy Combinations
610
Table 8-3. User-Programmable Flash Memory Resident Registers
614
Eeprom
615
Table 8-4. MEMTIM0 Register Configuration Versus Frequency
617
Bus Matrix Memory Accesses
621
Table 8-6. Flash Register Map
622
Internal Memory Register Descriptions (Internal Memory Control Offset)
624
Register 1: Flash Memory Address (FMA), Offset 0X000
625
Register 2: Flash Memory Data (FMD), Offset 0X004
626
Register 3: Flash Memory Control (FMC), Offset 0X008
627
Register 4: Flash Controller Raw Interrupt Status (FCRIS), Offset 0X00C
630
Register 5: Flash Controller Interrupt Mask (FCIM), Offset 0X010
633
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), Offset 0X014
635
Register 7: Flash Memory Control 2 (FMC2), Offset 0X020
638
Register 8: Flash Write Buffer Valid (FWBVAL), Offset 0X030
639
Register 9: Flash Program/Erase Key (FLPEKEY), Offset 0X03C
640
Register 10: Flash Write Buffer N (Fwbn), Offset 0X100 - 0X17C
641
Register 11: Flash Peripheral Properties (FLASHPP), Offset 0Xfc0
642
Register 12: SRAM Size (SSIZE), Offset 0Xfc4
644
Register 13: Flash Configuration Register (FLASHCONF), Offset 0Xfc8
645
Register 14: ROM Third-Party Software (ROMSWMAP), Offset 0Xfcc
647
Register 15: Flash DMA Address Size (FLASHDMASZ), Offset 0Xfd0
649
Register 16: Flash DMA Starting Address (FLASHDMAST), Offset 0Xfd4
650
EEPROM Register Descriptions (EEPROM Offset)
650
Register 17: EEPROM Size Information (EESIZE), Offset 0X000
651
Register 18: EEPROM Current Block (EEBLOCK), Offset 0X004
652
Register 19: EEPROM Current Offset (EEOFFSET), Offset 0X008
653
Register 20: EEPROM Read-Write (EERDWR), Offset 0X010
654
Register 21: EEPROM Read-Write with Increment (EERDWRINC), Offset 0X014
655
Register 22: EEPROM Done Status (EEDONE), Offset 0X018
656
Register 23: EEPROM Support Control and Status (EESUPP), Offset 0X01C
658
Register 24: EEPROM Unlock (EEUNLOCK), Offset 0X020
659
Register 25: EEPROM Protection (EEPROT), Offset 0X030
660
Register 26: EEPROM Password (EEPASS0), Offset 0X034
662
Register 29: EEPROM Interrupt (EEINT), Offset 0X040
663
Register 30: EEPROM Block Hide 0 (EEHIDE0), Offset 0X050
664
Register 31: EEPROM Block Hide 1 (EEHIDE1), Offset 0X054
665
Memory Register Descriptions (System Control Offset)
667
Register 35: Reset Vector Pointer (RVP), Offset 0X0D4
668
Register 36: Flash Memory Protection Read Enable 0 (FMPRE0), Offset 0X200
669
Register 52: Flash Memory Protection Program Enable 0 (FMPPE0), Offset 0X400
671
Register 68: Boot Configuration (BOOTCFG), Offset 0X1D0
674
Register 71: User Register 2 (USER_REG2), Offset 0X1E8
677
Register 72: User Register 3 (USER_REG3), Offset 0X1Ec
677
Register 69: User Register 0 (USER_REG0), Offset 0X1E0
677
Micro Direct Memory Access (Μdma)
678
Block Diagram
679
Functional Description
679
Channel Assignments
680
Priority
681
Arbitration Size
682
Request Types
682
Channel Configuration
683
Table 9-3. Control Structure Memory Map
684
Transfer Modes
685
Figure 9-2. Example of Ping-Pong Μdma Transaction
686
Figure 9-3. Memory Scatter-Gather, Setup and Configuration
688
Figure 9-4. Memory Scatter-Gather, Μdma Copy Sequence
689
Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration
691
Figure 9-6. Peripheral Scatter-Gather, Μdma Copy Sequence
692
Peripheral Interface
693
Transfer Size and Increment
693
Initialization and Configuration
694
Interrupts and Errors
694
Module Initialization
694
Software Request
694
Configuring a Memory-To-Memory Transfer
695
Configuring a Peripheral for Simple Transmit
696
Table 9-9. Channel Control Structure Offsets for Channel 7
697
Configuring a Peripheral for Ping-Pong Receive
698
Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8
699
Configuring Channel Assignments
701
Register Map
701
Μdma Channel Control Structure
702
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), Offset 0X000
703
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), Offset 0X004
704
Register 3: DMA Channel Control Word (DMACHCTL), Offset 0X008
705
Μdma Register Descriptions
709
Register 4: DMA Status (DMASTAT), Offset 0X000
710
Register 5: DMA Configuration (DMACFG), Offset 0X004
712
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), Offset 0X008
713
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), Offset 0X00C
714
Register 8: DMA Channel Wait-On-Request Status (DMAWAITSTAT), Offset 0X010
715
Register 9: DMA Channel Software Request (DMASWREQ), Offset 0X014
716
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), Offset 0X018
717
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), Offset 0X01C
718
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), Offset 0X020
719
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), Offset 0X024
720
Register 14: DMA Channel Enable Set (DMAENASET), Offset 0X028
721
Register 15: DMA Channel Enable Clear (DMAENACLR), Offset 0X02C
722
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), Offset 0X030
723
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), Offset 0X034
724
Register 18: DMA Channel Priority Set (DMAPRIOSET), Offset 0X038
725
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), Offset 0X03C
726
Register 20: DMA Bus Error Clear (DMAERRCLR), Offset 0X04C
727
Register 21: DMA Channel Assignment (DMACHASGN), Offset 0X500
728
Register 22: DMA Channel Map Select 0 (DMACHMAP0), Offset 0X510
729
Register 23: DMA Channel Map Select 1 (DMACHMAP1), Offset 0X514
730
Register 24: DMA Channel Map Select 2 (DMACHMAP2), Offset 0X518
731
Register 25: DMA Channel Map Select 3 (DMACHMAP3), Offset 0X51C
732
Register 26: DMA Peripheral Identification 0 (Dmaperiphid0), Offset 0Xfe0
733
Register 27: DMA Peripheral Identification 1 (Dmaperiphid1), Offset 0Xfe4
734
Register 28: DMA Peripheral Identification 2 (Dmaperiphid2), Offset 0Xfe8
735
Register 29: DMA Peripheral Identification 3 (Dmaperiphid3), Offset 0Xfec
736
Register 30: DMA Peripheral Identification 4 (Dmaperiphid4), Offset 0Xfd0
737
Register 31: DMA Primecell Identification 0 (Dmapcellid0), Offset 0Xff0
738
Register 32: DMA Primecell Identification 1 (Dmapcellid1), Offset 0Xff4
739
Register 33: DMA Primecell Identification 2 (Dmapcellid2), Offset 0Xff8
740
Register 34: DMA Primecell Identification 3 (Dmapcellid3), Offset 0Xffc
741
General-Purpose Input/Outputs (Gpios)
742
Signal Description
743
Pad Capabilities
746
Functional Description
747
Data Control
748
Figure 10-3. GPIODATA Write Example
749
Interrupt Control
750
Mode Control
751
Commit Control
752
Pad Control
752
Identification
753
Initialization and Configuration
753
Table 10-4. GPIO Pad Configuration Examples
754
Register Map
755
Table 10-6. GPIO Pins with Special Considerations
756
Table 10-7. GPIO Register Map
757
Register Descriptions
758
Register 1: GPIO Data (GPIODATA), Offset 0X000
759
Register 2: GPIO Direction (GPIODIR), Offset 0X400
760
Register 3: GPIO Interrupt Sense (GPIOIS), Offset 0X404
761
Register 4: GPIO Interrupt both Edges (GPIOIBE), Offset 0X408
762
Register 5: GPIO Interrupt Event (GPIOIEV), Offset 0X40C
763
Register 6: GPIO Interrupt Mask (GPIOIM), Offset 0X410
764
Register 7: GPIO Raw Interrupt Status (GPIORIS), Offset 0X414
765
Register 8: GPIO Masked Interrupt Status (GPIOMIS), Offset 0X418
767
Register 9: GPIO Interrupt Clear (GPIOICR), Offset 0X41C
769
Register 10: GPIO Alternate Function Select (GPIOAFSEL), Offset 0X420
770
Table 10-8. GPIO Pins with Special Considerations
770
Register 11: GPIO 2-Ma Drive Select (GPIODR2R), Offset 0X500
772
Register 12: GPIO 4-Ma Drive Select (GPIODR4R), Offset 0X504
773
Register 13: GPIO 8-Ma Drive Select (GPIODR8R), Offset 0X508
774
Register 14: GPIO Open Drain Select (GPIOODR), Offset 0X50C
775
Register 15: GPIO Pull-Up Select (GPIOPUR), Offset 0X510
776
Table 10-9. GPIO Pins with Special Considerations
776
Register 16: GPIO Pull-Down Select (GPIOPDR), Offset 0X514
778
Table 10-10. GPIO Pins with Special Considerations
778
Register 17: GPIO Slew Rate Control Select (GPIOSLR), Offset 0X518
780
Register 18: GPIO Digital Enable (GPIODEN), Offset 0X51C
781
Table 10-11. GPIO Pins with Special Considerations
781
Register 19: GPIO Lock (GPIOLOCK), Offset 0X520
783
Register 20: GPIO Commit (GPIOCR), Offset 0X524
784
Register 21: GPIO Analog Mode Select (GPIOAMSEL), Offset 0X528
786
Register 22: GPIO Port Control (GPIOPCTL), Offset 0X52C
787
Table 10-12. GPIO Pins with Special Considerations
787
Register 23: GPIO ADC Control (GPIOADCCTL), Offset 0X530
789
Register 24: GPIO DMA Control (GPIODMACTL), Offset 0X534
790
Register 25: GPIO Select Interrupt (GPIOSI), Offset 0X538
791
Register 26: GPIO 12-Ma Drive Select (GPIODR12R), Offset 0X53C
792
Register 27: GPIO Wake Pin Enable (GPIOWAKEPEN), Offset 0X540
793
Register 28: GPIO Wake Level (GPIOWAKELVL), Offset 0X544
795
Register 29: GPIO Wake Status (GPIOWAKESTAT), Offset 0X548
797
Register 30: GPIO Peripheral Property (GPIOPP), Offset 0Xfc0
799
Register 31: GPIO Peripheral Configuration (GPIOPC), Offset 0Xfc4
800
Table 10-13. GPIO Drive Strength Options
800
Register 32: GPIO Peripheral Identification 4 (Gpioperiphid4), Offset 0Xfd0
803
Register 33: GPIO Peripheral Identification 5 (Gpioperiphid5), Offset 0Xfd4
804
Register 34: GPIO Peripheral Identification 6 (Gpioperiphid6), Offset 0Xfd8
805
Register 35: GPIO Peripheral Identification 7 (Gpioperiphid7), Offset 0Xfdc
806
Register 36: GPIO Peripheral Identification 0 (Gpioperiphid0), Offset 0Xfe0
807
Register 37: GPIO Peripheral Identification 1 (Gpioperiphid1), Offset 0Xfe4
808
Register 38: GPIO Peripheral Identification 2 (Gpioperiphid2), Offset 0Xfe8
809
Register 39: GPIO Peripheral Identification 3 (Gpioperiphid3), Offset 0Xfec
810
Register 40: GPIO Primecell Identification 0 (Gpiopcellid0), Offset 0Xff0
811
Register 41: GPIO Primecell Identification 1 (Gpiopcellid1), Offset 0Xff4
812
Register 42: GPIO Primecell Identification 2 (Gpiopcellid2), Offset 0Xff8
813
Register 43: GPIO Primecell Identification 3 (Gpiopcellid3), Offset 0Xffc
814
External Peripheral Interface (EPI)
815
EPI Block Diagram
816
Signal Description
817
Functional Description
818
Master Access to EPI
819
Non-Blocking Reads
819
DMA Operation
820
Initialization and Configuration
821
EPI Interface Options
822
SDRAM Mode
822
Table 11-3. EPI SDRAM X16 Signal Connections
823
Figure 11-2. SDRAM Non-Blocking Read Cycle
824
Figure 11-3. SDRAM Normal Read Cycle
825
Host Bus Mode
826
Table 11-4. CSCFGEXT + CSCFG Encodings
827
Table 11-5. Dual- and Quad- Chip Select Address Mappings
828
Table 11-6. Chip Select Configuration Register Assignment
829
Table 11-8. EPI Host-Bus 8 Signal Connections
831
Table 11-9. EPI Host-Bus 16 Signal Connections
833
Figure 11-5. Irdy Access Stalls, IRDYDLY==01, 10, 11
836
Table 11-10. PSRAM Fixed Latency Wait State Configuration
838
Figure 11-7. PSRAM Burst Read
839
Figure 11-9. Read Delay During Refresh Event
840
Figure 11-10. Write Delay During Refresh Event
841
Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode
842
Table 11-11. Data Phase Wait State Programming
843
Figure 11-12. Host-Bus Read Cycle, MODE = 0X1, WRHIGH = 0, RDHIGH = 0
845
Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0X0, WRHIGH 0, RDHIGH = 0
846
General-Purpose Mode
847
Table 11-12. EPI General-Purpose Signal Connections
849
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0
850
Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1
851
Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0
852
Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1
853
Register Map
854
Register Descriptions
856
Register 1: EPI Configuration (EPICFG), Offset 0X000
857
Register 2: EPI Main Baud Rate (EPIBAUD), Offset 0X004
859
Register 3: EPI Main Baud Rate (EPIBAUD2), Offset 0X008
861
Register 4: EPI SDRAM Configuration (EPISDRAMCFG), Offset 0X010
863
Register 5: EPI Host-Bus 8 Configuration (EPIHB8CFG), Offset 0X010
865
Register 6: EPI Host-Bus 16 Configuration (EPIHB16CFG), Offset 0X010
870
Register 7: EPI General-Purpose Configuration (EPIGPCFG), Offset 0X010
876
Register 8: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), Offset 0X014
879
Table 11-14. CSCFGEXT + CSCFG Encodings
880
Register 9: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), Offset 0X014
885
Table 11-15. CSCFGEXT + CSCFG Encodings
886
Register 10: EPI Address Map (EPIADDRMAP), Offset 0X01C
892
Register 11: EPI Read Size 0 (EPIRSIZE0), Offset 0X020
895
Register 12: EPI Read Size 1 (EPIRSIZE1), Offset 0X030
895
Register 13: EPI Read Address 0 (EPIRADDR0), Offset 0X024
896
Register 14: EPI Read Address 1 (EPIRADDR1), Offset 0X034
896
Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), Offset 0X028
897
Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), Offset 0X038
897
Register 17: EPI Status (EPISTAT), Offset 0X060
899
Register 18: EPI Read FIFO Count (EPIRFIFOCNT), Offset 0X06C
901
Register 19: EPI Read FIFO (EPIREADFIFO0), Offset 0X070
902
Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), Offset 0X074
902
Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), Offset 0X078
902
Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), Offset 0X07C
902
Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), Offset 0X080
902
Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), Offset 0X084
902
Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), Offset 0X088
902
Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), Offset 0X08C
902
Register 27: EPI FIFO Level Selects (EPIFIFOLVL), Offset 0X200
903
Register 28: EPI Write FIFO Count (EPIWFIFOCNT), Offset 0X204
905
Register 29: EPI DMA Transmit Count (EPIDMATXCNT), Offset 0X208
906
Register 30: EPI Interrupt Mask (EPIIM), Offset 0X210
907
Register 31: EPI Raw Interrupt Status (EPIRIS), Offset 0X214
909
Register 32: EPI Masked Interrupt Status (EPIMIS), Offset 0X218
911
Register 33: EPI Error and Interrupt Status and Clear (EPIEISC), Offset 0X21C
913
Register 34: EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), Offset 0X308
915
Register 35: EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), Offset 0X308
918
Register 36: EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), Offset 0X30C
922
Register 37: EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), Offset 0X30C
925
Register 38: EPI Host-Bus 8 Timing Extension (EPIHB8TIME), Offset 0X310
929
Register 39: EPI Host-Bus 16 Timing Extension (EPIHB16TIME), Offset 0X310
931
Register 40: EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), Offset 0X314
933
Register 41: EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), Offset 0X314
935
Register 42: EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), Offset 0X318
937
Register 43: EPI Host-Bus 16 Timing Extension (EPIHB16TIME3), Offset 0X318
939
Register 44: EPI Host-Bus 8 Timing Extension (EPIHB8TIME4), Offset 0X31C
941
Register 45: EPI Host-Bus 16 Timing Extension (EPIHB16TIME4), Offset 0X31C
943
Register 46: EPI Host-Bus PSRAM (EPIHBPSRAM), Offset 0X360
945
Cyclical Redundancy Check (CRC)
946
CRC Support
946
Functional Description
946
Table 12-1. Endian Configuration
947
CRC Initialization and Configuration
948
Initialization and Configuration
948
CRC Module Register Descriptions
949
Register Map
949
Register 1: CRC Control (CRCCTRL), Offset 0X400
950
Register 2: CRC Seed/Context (CRCSEED), Offset 0X410
952
Register 3: CRC Data Input (CRCDIN), Offset 0X414
953
Register 4: CRC Post Processing Result (CRCRSLTPP), Offset 0X418
954
General-Purpose Timers
955
Block Diagram
956
Signal Description
957
Functional Description
958
GPTM Reset Conditions
959
Timer Clock Source
959
Timer Modes
959
Table 13-4. Counter Values When the Timer Is Enabled in Periodic or One-Shot Modes
960
Table 13-5. 16-Bit Timer with Prescaler Configurations
961
Table 13-6. Counter Values When the Timer Is Enabled in RTC Mode
962
Table 13-7. Counter Values When the Timer Is Enabled in Input Edge-Count Mode
963
Figure 13-2. Input Edge-Count Mode Example, Counting down
964
Figure 13-3. 16-Bit Input Edge-Time Mode Example
965
Table 13-9. Counter Values When the Timer Is Enabled in PWM Mode
966
Figure 13-4. 16-Bit PWM Mode Example
967
Wait-For-Trigger Mode
968
Synchronizing GP Timer Blocks
969
Accessing Concatenated 16/32-Bit GPTM Register Values
970
ADC Operation
970
DMA Operation
970
Initialization and Configuration
971
One-Shot/Periodic Timer Mode
971
Input Edge-Count Mode
972
Real-Time Clock (RTC) Mode
972
Input Edge Time Mode
973
PWM Mode
973
Register Map
974
Register Descriptions
975
Register 1: GPTM Configuration (GPTMCFG), Offset 0X000
976
Register 2: GPTM Timer a Mode (GPTMTAMR), Offset 0X004
977
Register 3: GPTM Timer B Mode (GPTMTBMR), Offset 0X008
982
Register 4: GPTM Control (GPTMCTL), Offset 0X00C
986
Register 5: GPTM Synchronize (GPTMSYNC), Offset 0X010
990
Register 6: GPTM Interrupt Mask (GPTMIMR), Offset 0X018
993
Register 7: GPTM Raw Interrupt Status (GPTMRIS), Offset 0X01C
996
Register 8: GPTM Masked Interrupt Status (GPTMMIS), Offset 0X020
999
Register 9: GPTM Interrupt Clear (GPTMICR), Offset 0X024
1002
Register 10: GPTM Timer a Interval Load (GPTMTAILR), Offset 0X028
1004
Register 11: GPTM Timer B Interval Load (GPTMTBILR), Offset 0X02C
1005
Register 12: GPTM Timer a Match (GPTMTAMATCHR), Offset 0X030
1006
Register 13: GPTM Timer B Match (GPTMTBMATCHR), Offset 0X034
1007
Register 14: GPTM Timer a Prescale (GPTMTAPR), Offset 0X038
1008
Register 15: GPTM Timer B Prescale (GPTMTBPR), Offset 0X03C
1009
Register 16: GPTM Timera Prescale Match (GPTMTAPMR), Offset 0X040
1010
Register 17: GPTM Timerb Prescale Match (GPTMTBPMR), Offset 0X044
1011
Register 18: GPTM Timer a (GPTMTAR), Offset 0X048
1012
Register 19: GPTM Timer B (GPTMTBR), Offset 0X04C
1013
Register 20: GPTM Timer a Value (GPTMTAV), Offset 0X050
1014
Register 21: GPTM Timer B Value (GPTMTBV), Offset 0X054
1015
Register 22: GPTM RTC Predivide (GPTMRTCPD), Offset 0X058
1016
Register 23: GPTM Timer a Prescale Snapshot (GPTMTAPS), Offset 0X05C
1017
Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), Offset 0X060
1018
Register 25: GPTM DMA Event (GPTMDMAEV), Offset 0X06C
1019
Register 26: GPTM ADC Event (GPTMADCEV), Offset 0X070
1022
Register 27: GPTM Peripheral Properties (GPTMPP), Offset 0Xfc0
1025
Register 28: GPTM Clock Configuration (GPTMCC), Offset 0Xfc8
1027
Watchdog Timers
1028
Block Diagram
1029
Functional Description
1029
Initialization and Configuration
1030
Register Access Timing
1030
Register Map
1030
Register Descriptions
1031
Register 1: Watchdog Load (WDTLOAD), Offset 0X000
1032
Register 2: Watchdog Value (WDTVALUE), Offset 0X004
1033
Register 3: Watchdog Control (WDTCTL), Offset 0X008
1034
Register 4: Watchdog Interrupt Clear (WDTICR), Offset 0X00C
1036
Register 5: Watchdog Raw Interrupt Status (WDTRIS), Offset 0X010
1037
Register 6: Watchdog Masked Interrupt Status (WDTMIS), Offset 0X014
1038
Register 7: Watchdog Test (WDTTEST), Offset 0X418
1039
Register 8: Watchdog Lock (WDTLOCK), Offset 0Xc00
1040
Register 9: Watchdog Peripheral Identification 4 (Wdtperiphid4), Offset 0Xfd0
1041
Register 10: Watchdog Peripheral Identification 5 (Wdtperiphid5), Offset 0Xfd4
1042
Register 11: Watchdog Peripheral Identification 6 (Wdtperiphid6), Offset 0Xfd8
1043
Register 12: Watchdog Peripheral Identification 7 (Wdtperiphid7), Offset 0Xfdc
1044
Register 13: Watchdog Peripheral Identification 0 (Wdtperiphid0), Offset 0Xfe0
1045
Register 14: Watchdog Peripheral Identification 1 (Wdtperiphid1), Offset 0Xfe4
1046
Register 15: Watchdog Peripheral Identification 2 (Wdtperiphid2), Offset 0Xfe8
1047
Register 16: Watchdog Peripheral Identification 3 (Wdtperiphid3), Offset 0Xfec
1048
Register 17: Watchdog Primecell Identification 0 (Wdtpcellid0), Offset 0Xff0
1049
Register 18: Watchdog Primecell Identification 1 (Wdtpcellid1), Offset 0Xff4
1050
Register 19: Watchdog Primecell Identification 2 (Wdtpcellid2), Offset 0Xff8
1051
Register 20: Watchdog Primecell Identification 3 (Wdtpcellid3 ), Offset 0Xffc
1052
Analog-To-Digital Converter (ADC)
1053
Block Diagram
1054
Signal Description
1055
Functional Description
1056
Sample Sequencers
1056
Module Control
1057
Table 15-3. Sample and Hold Width in ADC Clocks
1058
Figure 15-3. ADC Sample Phases
1060
Figure 15-5. Skewed Sampling
1061
Hardware Sample Averaging Circuit
1062
Analog-To-Digital Converter
1063
Figure 15-7. ADC Input Equivalency
1064
Differential Sampling
1065
Table 15-6. Differential Sampling Pairs
1066
Internal Temperature Sensor
1067
Digital Comparator Unit
1068
Figure 15-12. Low-Band Operation (CIC=0X0 And/Or Ctc=0X0)
1070
Figure 15-13. MID-Band Operation (CIC=0X1 And/Or Ctc=0X1)
1071
Initialization and Configuration
1072
Module Initialization
1072
Register Map
1073
Sample Sequencer Configuration
1073
Register Descriptions
1076
Register 1: ADC Active Sample Sequencer (ADCACTSS), Offset 0X000
1077
Register 2: ADC Raw Interrupt Status (ADCRIS), Offset 0X004
1079
Register 3: ADC Interrupt Mask (ADCIM), Offset 0X008
1082
Register 4: ADC Interrupt Status and Clear (ADCISC), Offset 0X00C
1085
Register 5: ADC Overflow Status (ADCOSTAT), Offset 0X010
1089
Register 6: ADC Event Multiplexer Select (ADCEMUX), Offset 0X014
1091
Register 7: ADC Underflow Status (ADCUSTAT), Offset 0X018
1096
Register 8: ADC Trigger Source Select (ADCTSSEL), Offset 0X01C
1097
Register 9: ADC Sample Sequencer Priority (ADCSSPRI), Offset 0X020
1099
Register 10: ADC Sample Phase Control (ADCSPC), Offset 0X024
1101
Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), Offset 0X028
1103
Register 12: ADC Sample Averaging Control (ADCSAC), Offset 0X030
1105
Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), Offset 0X034
1106
Register 14: ADC Control (ADCCTL), Offset 0X038
1108
Register 15: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), Offset 0X040
1109
Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), Offset 0X044
1111
Register 17: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), Offset 0X048
1118
Register 18: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), Offset 0X068
1118
Register 19: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), Offset 0X088
1118
Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), Offset 0X0A8
1118
Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), Offset 0X04C
1119
Register 22: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), Offset 0X06C
1119
Register 23: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), Offset 0X08C
1119
Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), Offset 0X0Ac
1119
Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), Offset 0X050
1121
Register 26: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), Offset 0X054
1123
Register 27: ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0), Offset 0X058
1125
Register 28: ADC Sample Sequence 0 Sample and Hold Time (ADCSSTSH0), Offset 0X05C
1127
Table 15-8. Sample and Hold Width in ADC Clocks
1127
Register 29: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), Offset 0X060
1129
Register 30: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), Offset 0X080
1129
Register 31: ADC Sample Sequence Control 1 (ADCSSCTL1), Offset 0X064
1130
Register 32: ADC Sample Sequence Control 2 (ADCSSCTL2), Offset 0X084
1130
Register 33: ADC Sample Sequence 1 Operation (ADCSSOP1), Offset 0X070
1134
Register 34: ADC Sample Sequence 2 Operation (ADCSSOP2), Offset 0X090
1134
Register 35: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), Offset 0X074
1135
Register 36: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), Offset 0X094
1135
Register 37: ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), Offset 0X078
1137
Register 38: ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), Offset 0X098
1137
Register 39: ADC Sample Sequence 1 Sample and Hold Time (ADCSSTSH1), Offset 0X07C
1139
Register 40: ADC Sample Sequence 2 Sample and Hold Time (ADCSSTSH2), Offset 0X09C
1139
Table 15-9. Sample and Hold Width in ADC Clocks
1139
Register 41: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), Offset 0X0A0
1141
Register 42: ADC Sample Sequence Control 3 (ADCSSCTL3), Offset 0X0A4
1142
Register 43: ADC Sample Sequence 3 Operation (ADCSSOP3), Offset 0X0B0
1144
Register 44: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), Offset 0X0B4
1145
Register 45: ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), Offset 0X0B8
1146
Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3), Offset 0X0Bc
1147
Table 15-10. Sample and Hold Width in ADC Clocks
1147
Register 47: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), Offset 0Xd00
1148
Register 48: ADC Digital Comparator Control 0 (ADCDCCTL0), Offset 0Xe00
1153
Register 49: ADC Digital Comparator Control 1 (ADCDCCTL1), Offset 0Xe04
1153
Register 50: ADC Digital Comparator Control 2 (ADCDCCTL2), Offset 0Xe08
1153
Register 51: ADC Digital Comparator Control 3 (ADCDCCTL3), Offset 0Xe0C
1153
Register 52: ADC Digital Comparator Control 4 (ADCDCCTL4), Offset 0Xe10
1153
Register 53: ADC Digital Comparator Control 5 (ADCDCCTL5), Offset 0Xe14
1153
Register 54: ADC Digital Comparator Control 6 (ADCDCCTL6), Offset 0Xe18
1153
Register 55: ADC Digital Comparator Control 7 (ADCDCCTL7), Offset 0Xe1C
1153
Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), Offset 0Xe40
1156
Register 57: ADC Digital Comparator Range 1 (ADCDCCMP1), Offset 0Xe44
1156
Register 58: ADC Digital Comparator Range 2 (ADCDCCMP2), Offset 0Xe48
1156
Register 59: ADC Digital Comparator Range 3 (ADCDCCMP3), Offset 0Xe4C
1156
Register 60: ADC Digital Comparator Range 4 (ADCDCCMP4), Offset 0Xe50
1156
Register 61: ADC Digital Comparator Range 5 (ADCDCCMP5), Offset 0Xe54
1156
Register 62: ADC Digital Comparator Range 6 (ADCDCCMP6), Offset 0Xe58
1156
Register 63: ADC Digital Comparator Range 7 (ADCDCCMP7), Offset 0Xe5C
1156
Register 64: ADC Peripheral Properties (ADCPP), Offset 0Xfc0
1157
Register 65: ADC Peripheral Configuration (ADCPC), Offset 0Xfc4
1159
Register 66: ADC Clock Configuration (ADCCC), Offset 0Xfc8
1160
Universal Asynchronous Receivers/Transmitters (Uarts)
1161
Block Diagram
1162
Signal Description
1162
Table 16-1. UART Signals (128TQFP)
1163
Functional Description
1164
Transmit/Receive Logic
1164
Baud-Rate Generation
1165
Data Transmission
1166
Serial IR (SIR)
1166
ISO 7816 Support
1167
Modem Handshake Support
1168
9-Bit UART Mode
1169
FIFO Operation
1169
Interrupts
1170
DMA Operation
1171
Loopback Operation
1171
Initialization and Configuration
1172
Register Map
1173
Register Descriptions
1174
Register 1: UART Data (UARTDR), Offset 0X000
1175
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), Offset 0X004
1177
Register 3: UART Flag (UARTFR), Offset 0X018
1180
Register 4: UART Irda Low-Power Register (UARTILPR), Offset 0X020
1183
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), Offset 0X024
1184
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), Offset 0X028
1185
Register 7: UART Line Control (UARTLCRH), Offset 0X02C
1186
Register 8: UART Control (UARTCTL), Offset 0X030
1188
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), Offset 0X034
1192
Register 10: UART Interrupt Mask (UARTIM), Offset 0X038
1194
Register 11: UART Raw Interrupt Status (UARTRIS), Offset 0X03C
1198
Register 12: UART Masked Interrupt Status (UARTMIS), Offset 0X040
1202
Register 13: UART Interrupt Clear (UARTICR), Offset 0X044
1206
Register 14: UART DMA Control (UARTDMACTL), Offset 0X048
1208
Register 15: UART 9-Bit Self Address (UART9BITADDR), Offset 0X0A4
1209
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), Offset 0X0A8
1210
Register 17: UART Peripheral Properties (UARTPP), Offset 0Xfc0
1211
Register 18: UART Clock Configuration (UARTCC), Offset 0Xfc8
1213
Register 19: UART Peripheral Identification 4 (Uartperiphid4), Offset 0Xfd0
1214
Register 20: UART Peripheral Identification 5 (Uartperiphid5), Offset 0Xfd4
1215
Register 21: UART Peripheral Identification 6 (Uartperiphid6), Offset 0Xfd8
1216
Register 22: UART Peripheral Identification 7 (Uartperiphid7), Offset 0Xfdc
1217
Register 23: UART Peripheral Identification 0 (Uartperiphid0), Offset 0Xfe0
1218
Register 24: UART Peripheral Identification 1 (Uartperiphid1), Offset 0Xfe4
1219
Register 25: UART Peripheral Identification 2 (Uartperiphid2), Offset 0Xfe8
1220
Register 26: UART Peripheral Identification 3 (Uartperiphid3), Offset 0Xfec
1221
Register 27: UART Primecell Identification 0 (Uartpcellid0), Offset 0Xff0
1222
Register 28: UART Primecell Identification 1 (Uartpcellid1), Offset 0Xff4
1223
Register 29: UART Primecell Identification 2 (Uartpcellid2), Offset 0Xff8
1224
Register 30: UART Primecell Identification 3 (Uartpcellid3), Offset 0Xffc
1225
Quad Synchronous Serial Interface (QSSI)
1226
Block Diagram
1226
Signal Description
1227
Functional Description
1228
Bit Rate Generation
1229
FIFO Operation
1229
Advanced, Bi- and Quad- SSI Function
1230
Ssinfss Function
1231
High Speed Clock Operation
1232
Interrupts
1232
Frame Formats
1233
Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer)
1234
Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer)
1235
Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
1236
Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1
1237
Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
1238
Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1
1239
DMA Operation
1240
Initialization and Configuration
1240
Enhanced Mode Configuration
1242
Register Map
1243
Register Descriptions
1244
Register 1: QSSI Control 0 (SSICR0), Offset 0X000
1245
Register 2: QSSI Control 1 (SSICR1), Offset 0X004
1247
Register 3: QSSI Data (SSIDR), Offset 0X008
1249
Register 4: QSSI Status (SSISR), Offset 0X00C
1250
Register 5: QSSI Clock Prescale (SSICPSR), Offset 0X010
1252
Register 6: QSSI Interrupt Mask (SSIIM), Offset 0X014
1253
Register 7: QSSI Raw Interrupt Status (SSIRIS), Offset 0X018
1255
Register 8: QSSI Masked Interrupt Status (SSIMIS), Offset 0X01C
1257
Register 9: QSSI Interrupt Clear (SSIICR), Offset 0X020
1259
Register 10: QSSI DMA Control (SSIDMACTL), Offset 0X024
1260
Register 11: QSSI Peripheral Properties (SSIPP), Offset 0Xfc0
1261
Register 12: QSSI Clock Configuration (SSICC), Offset 0Xfc8
1262
Register 13: QSSI Peripheral Identification 4 (Ssiperiphid4), Offset 0Xfd0
1263
Register 14: QSSI Peripheral Identification 5 (Ssiperiphid5), Offset 0Xfd4
1264
Register 15: QSSI Peripheral Identification 6 (Ssiperiphid6), Offset 0Xfd8
1265
Register 16: QSSI Peripheral Identification 7 (Ssiperiphid7), Offset 0Xfdc
1266
Register 17: QSSI Peripheral Identification 0 (Ssiperiphid0), Offset 0Xfe0
1267
Register 18: QSSI Peripheral Identification 1 (Ssiperiphid1), Offset 0Xfe4
1268
Register 19: QSSI Peripheral Identification 2 (Ssiperiphid2), Offset 0Xfe8
1269
Register 20: QSSI Peripheral Identification 3 (Ssiperiphid3), Offset 0Xfec
1270
Register 21: QSSI Primecell Identification 0 (Ssipcellid0), Offset 0Xff0
1271
Register 22: QSSI Primecell Identification 1 (Ssipcellid1), Offset 0Xff4
1272
Register 23: QSSI Primecell Identification 2 (Ssipcellid2), Offset 0Xff8
1273
Register 24: QSSI Primecell Identification 3 (Ssipcellid3), Offset 0Xffc
1274
Inter-Integrated Circuit (I 2 C) Interface
1275
Block Diagram
1276
Signal Description
1277
Functional Description
1278
I 2 C Bus Functional Overview
1278
Figure 18-3. START and STOP Conditions
1279
Figure 18-5. R/S Bit in First Byte
1280
Available Speed Modes
1284
Interrupts
1286
FIFO and Μdma Operation
1287
Loopback Operation
1287
Command Sequence Flow Charts
1289
Figure 18-8. Master Single TRANSMIT
1290
Figure 18-9. Master Single RECEIVE
1291
Figure 18-10. Master TRANSMIT of Multiple Data Bytes
1292
Figure 18-11. Master RECEIVE of Multiple Data Bytes
1293
Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT
1294
Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE
1295
Figure 18-14. Standard High Speed Mode Master Transmit
1296
Initialization and Configuration
1297
Register Map
1299
Register 1: I C Master Slave Address (I2CMSA), Offset 0X000
1302
Register 2: I C Master Control/Status (I2CMCS), Offset 0X004
1303
Table 18-5. Write Field Decoding for I2CMCS[6:0]
1308
Register 3: I C Master Data (I2CMDR), Offset 0X008
1312
Register 4: I C Master Timer Period (I2CMTPR), Offset 0X00C
1313
Register 5: I C Master Interrupt Mask (I2CMIMR), Offset 0X010
1315
Register 6: I C Master Raw Interrupt Status (I2CMRIS), Offset 0X014
1318
Register 7: I C Master Masked Interrupt Status (I2CMMIS), Offset 0X018
1321
Register 8: I C Master Interrupt Clear (I2CMICR), Offset 0X01C
1324
Register 9: I C Master Configuration (I2CMCR), Offset 0X020
1326
Register 10: I 2 C Master Clock Low Timeout Count (I2CMCLKOCNT), Offset 0X024
1327
Register 11: I C Master Bus Monitor (I2CMBMON), Offset 0X02C
1328
Register 12: I C Master Burst Length (I2CMBLEN), Offset 0X030
1329
Register 13: I 2 C Master Burst Count (I2CMBCNT), Offset 0X034
1330
Register 14: I C Slave Own Address (I2CSOAR), Offset 0X800
1331
Register 15: I C Slave Control/Status (I2CSCSR), Offset 0X804
1332
Register 16: I C Slave Data (I2CSDR), Offset 0X808
1335
Register 17: I 2 C Slave Interrupt Mask (I2CSIMR), Offset 0X80C
1336
Register 18: I C Slave Raw Interrupt Status (I2CSRIS), Offset 0X810
1338
Register 19: I C Slave Masked Interrupt Status (I2CSMIS), Offset 0X814
1341
Register 20: I C Slave Interrupt Clear (I2CSICR), Offset 0X818
1344
Register 21: I C Slave Own Address 2 (I2CSOAR2), Offset 0X81C
1346
Register 22: I 2 C Slave ACK Control (I2CSACKCTL), Offset 0X820
1347
Register 23: I C FIFO Data (I2CFIFODATA), Offset 0Xf00
1348
Register 24: I C FIFO Control (I2CFIFOCTL), Offset 0Xf04
1350
Register 25: I C FIFO Status (I2CFIFOSTATUS), Offset 0Xf08
1352
Register 26: I C Peripheral Properties (I2CPP), Offset 0Xfc0
1354
Register 27: I C Peripheral Configuration (I2CPC), Offset 0Xfc4
1355
Controller Area Network (CAN) Module
1356
Block Diagram
1357
Functional Description
1358
Initialization
1359
Transmitting Message Objects
1360
Configuring a Transmit Message Object
1361
Updating a Transmit Message Object
1362
Receiving a Data Frame
1363
Configuring a Receive Message Object
1364
Handling of Received Message Objects
1365
Handling of Interrupts
1367
Test Mode
1368
Bit Timing Configuration Error Considerations
1370
Figure 19-4. CAN Bit Time
1371
Calculating the Bit Timing Parameters
1372
Register Map
1375
CAN Register Descriptions
1376
Register 1: CAN Control (CANCTL), Offset 0X000
1378
Register 2: CAN Status (CANSTS), Offset 0X004
1380
Register 3: CAN Error Counter (CANERR), Offset 0X008
1383
Register 4: CAN Bit Timing (CANBIT), Offset 0X00C
1384
Register 5: CAN Interrupt (CANINT), Offset 0X010
1385
Register 6: CAN Test (CANTST), Offset 0X014
1386
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), Offset 0X018
1388
Register 8: CAN IF1 Command Request (CANIF1CRQ), Offset 0X020
1389
Register 9: CAN IF2 Command Request (CANIF2CRQ), Offset 0X080
1389
Register 10: CAN IF1 Command Mask (CANIF1CMSK), Offset 0X024
1390
Register 11: CAN IF2 Command Mask (CANIF2CMSK), Offset 0X084
1390
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), Offset 0X028
1393
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), Offset 0X088
1393
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), Offset 0X02C
1394
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), Offset 0X08C
1394
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), Offset 0X030
1396
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), Offset 0X090
1396
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), Offset 0X034
1397
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), Offset 0X094
1397
Register 20: CAN IF1 Message Control (CANIF1MCTL), Offset 0X038
1399
Register 21: CAN IF2 Message Control (CANIF2MCTL), Offset 0X098
1399
Register 22: CAN IF1 Data A1 (CANIF1DA1), Offset 0X03C
1402
Register 23: CAN IF1 Data A2 (CANIF1DA2), Offset 0X040
1402
Register 24: CAN IF1 Data B1 (CANIF1DB1), Offset 0X044
1402
Register 25: CAN IF1 Data B2 (CANIF1DB2), Offset 0X048
1402
Register 26: CAN IF2 Data A1 (CANIF2DA1), Offset 0X09C
1402
Register 27: CAN IF2 Data A2 (CANIF2DA2), Offset 0X0A0
1402
Register 28: CAN IF2 Data B1 (CANIF2DB1), Offset 0X0A4
1402
Register 29: CAN IF2 Data B2 (CANIF2DB2), Offset 0X0A8
1402
Register 30: CAN Transmission Request 1 (CANTXRQ1), Offset 0X100
1403
Register 31: CAN Transmission Request 2 (CANTXRQ2), Offset 0X104
1403
Register 32: CAN New Data 1 (CANNWDA1), Offset 0X120
1404
Register 33: CAN New Data 2 (CANNWDA2), Offset 0X124
1404
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), Offset 0X140
1405
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), Offset 0X144
1405
Register 36: CAN Message 1 Valid (CANMSG1VAL), Offset 0X160
1406
Register 37: CAN Message 2 Valid (CANMSG2VAL), Offset 0X164
1406
Ethernet Controller
1407
Block Diagram
1408
Functional Description
1409
DMA Controller
1410
Figure 20-3. Enhanced Transmit Descriptor Structure
1414
Table 20-3. Enhanced Transmit Descriptor 1 (TDES1)
1417
Table 20-4. Enhanced Transmit Descriptor 2 (TDES2)
1418
Figure 20-4. Enhanced Receive Descriptor Structure
1419
Table 20-9. RDES0 Checksum Offload Bits
1421
Table 20-10. Enhanced Receive Descriptor 1 (RDES1)
1422
Table 20-14. Enhanced Receive Descriptor 6 (RDES6)
1424
Figure 20-5. TX DMA Default Operation Using Descriptors
1426
Figure 20-6. TX DMA OSF Mode Operation Using Descriptors
1428
Figure 20-7. RX DMA Operation Flow
1431
TX/RX Controller
1434
Table 20-16. TX MAC Flow Control
1437
MAC Operation
1438
IEEE 1588 and Advanced Timestamp Function
1440
Figure 20-8. Networked Time Synchronization
1441
Figure 20-9. System Time Update Using Fine Correction Method
1443
Correction
1446
Frame Filtering
1449
Source Address, VLAN, and CRC Insertion, Replacement or Deletion
1450
Checksum Offload Engine
1452
MAC Management Counters
1453
Power Management Module
1454
Serial Management Interface
1457
Functional Description
1458
Table 20-21. Advertised Mode Configurations
1459
Interface Configuration
1463
Initialization and Configuration
1464
Ethernet PHY Initialization
1465
Register Map
1467
Ethernet MAC Register Descriptions
1470
Register 1: Ethernet MAC Configuration (EMACCFG), Offset 0X000
1471
Register 2: Ethernet MAC Frame Filter (EMACFRAMEFLTR), Offset 0X004
1478
Register 3: Ethernet MAC Hash Table High (EMACHASHTBLH), Offset 0X008
1482
Register 4: Ethernet MAC Hash Table Low (EMACHASHTBLL), Offset 0X00C
1483
Register 5: Ethernet MAC MII Address (EMACMIIADDR), Offset 0X010
1484
Register 6: Ethernet MAC MII Data Register (EMACMIIDATA), Offset 0X014
1486
Register 7: Ethernet MAC Flow Control (EMACFLOWCTL), Offset 0X018
1487
Register 8: Ethernet MAC VLAN Tag (EMACVLANTG), Offset 0X01C
1489
Register 9: Ethernet MAC Status (EMACSTATUS), Offset 0X024
1491
Register 10: Ethernet MAC Remote Wake-Up Frame Filter (EMACRWUFF), Offset 0X028
1494
Register 11: Ethernet MAC PMT Control and Status Register (EMACPMTCTLSTAT), Offset 0X02C
1495
Register 12: Ethernet MAC Raw Interrupt Status (EMACRIS), Offset 0X038
1497
Register 13: Ethernet MAC Interrupt Mask (EMACIM), Offset 0X03C
1499
Register 14: Ethernet MAC Address 0 High (EMACADDR0H), Offset 0X040
1500
Register 15: Ethernet MAC Address 0 Low Register (EMACADDR0L), Offset 0X044
1501
Register 16: Ethernet MAC Address 1 High (EMACADDR1H), Offset 0X048
1502
Register 17: Ethernet MAC Address 1 Low (EMACADDR1L), Offset 0X04C
1504
Register 18: Ethernet MAC Address 2 High (EMACADDR2H), Offset 0X050
1505
Register 19: Ethernet MAC Address 2 Low (EMACADDR2L), Offset 0X054
1507
Register 20: Ethernet MAC Address 3 High (EMACADDR3H), Offset 0X058
1508
Register 21: Ethernet MAC Address 3 Low (EMACADDR3L), Offset 0X05C
1510
Register 22: Ethernet MAC Watchdog Timeout (EMACWDOGTO), Offset 0X0Dc
1511
Register 23: Ethernet MAC MMC Control (EMACMMCCTRL), Offset 0X100
1512
Register 25: Ethernet MAC MMC Transmit Raw Interrupt Status (EMACMMCTXRIS), Offset 0X108
1517
Register 26: Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM), Offset 0X10C
1519
Register 27: Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM), Offset 0X110
1521
Register 28: Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB), Offset 0X118
1523
Register 29: Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision EMACTXCNTSCOL), Offset 0X14C
1524
Register 30: Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions EMACTXCNTMCOL), Offset 0X150
1525
Register 31: Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG), Offset 0X164
1526
Register 32: Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB), Offset 0X180
1527
Register 33: Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR), Offset 0X194
1528
Register 34: Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR Offset 0X198
1529
Register 35: Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI), Offset 0X1C4
1530
Register 36: Ethernet MAC VLAN Tag Inclusion or Replacement (EMACVLNINCREP), Offset 0X584
1531
Register 37: Ethernet MAC VLAN Hash Table (EMACVLANHASH), Offset 0X588
1533
Register 38: Ethernet MAC Timestamp Control (EMACTIMSTCTRL), Offset 0X700
1534
Register 39: Ethernet MAC Sub-Second Increment (EMACSUBSECINC), Offset 0X704
1538
Register 40: Ethernet MAC System Time - Seconds (EMACTIMSEC), Offset 0X708
1539
Register 41: Ethernet MAC System Time - Nanoseconds (EMACTIMNANO), Offset 0X70C
1540
Register 42: Ethernet MAC System Time - Seconds Update (EMACTIMSECU), Offset 0X710
1541
Register 43: Ethernet MAC System Time - Nanoseconds Update (EMACTIMNANOU), Offset 0X714
1542
Register 44: Ethernet MAC Timestamp Addend (EMACTIMADD), Offset 0X718
1543
Register 45: Ethernet MAC Target Time Seconds (EMACTARGSEC), Offset 0X71C
1544
Register 46: Ethernet MAC Target Time Nanoseconds (EMACTARGNANO), Offset 0X720
1545
Register 47: Ethernet MAC System Time-Higher Word Seconds (EMACHWORDSEC), Offset 0X724
1546
Register 48: Ethernet MAC Timestamp Status (EMACTIMSTAT), Offset 0X728
1547
Register 49: Ethernet MAC PPS Control (EMACPPSCTRL), Offset 0X72C
1548
Table 20-24. PPSCTRL Bit Field Values
1549
Register 50: Ethernet MAC PPS0 Interval (EMACPPS0INTVL), Offset 0X760
1551
Register 51: Ethernet MAC PPS0 Width (EMACPPS0WIDTH), Offset 0X764
1552
Register 52: Ethernet MAC DMA Bus Mode (EMACDMABUSMOD), Offset 0Xc00
1553
Register 53: Ethernet MAC Transmit Poll Demand (EMACTXPOLLD), Offset 0Xc04
1557
Register 54: Ethernet MAC Receive Poll Demand (EMACRXPOLLD), Offset 0Xc08
1558
Register 55: Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR), Offset 0Xc0C
1559
Register 56: Ethernet MAC Transmit Descriptor List Address (EMACTXDLADDR), Offset 0Xc10
1560
Register 57: Ethernet MAC DMA Interrupt Status (EMACDMARIS), Offset 0Xc14
1561
Register 58: Ethernet MAC DMA Operation Mode (EMACDMAOPMODE), Offset 0Xc18
1567
Register 59: Ethernet MAC DMA Interrupt Mask Register (EMACDMAIM), Offset 0Xc1C
1572
Register 60: Ethernet MAC Missed Frame and Buffer Overflow Counter (EMACMFBOC), Offset 0Xc20
1575
Register 61: Ethernet MAC Receive Interrupt Watchdog Timer (EMACRXINTWDT), Offset 0Xc24
1576
Register 62: Ethernet MAC Current Host Transmit Descriptor (EMACHOSTXDESC), Offset 0Xc48
1577
Register 63: Ethernet MAC Current Host Receive Descriptor (EMACHOSRXDESC), Offset 0Xc4C
1578
Register 64: Ethernet MAC Current Host Transmit Buffer Address (EMACHOSTXBA), Offset 0Xc50
1579
Register 65: Ethernet MAC Current Host Receive Buffer Address (EMACHOSRXBA), Offset 0Xc54
1580
Register 66: Ethernet MAC Peripheral Property Register (EMACPP), Offset 0Xfc0
1581
Register 67: Ethernet MAC Peripheral Configuration Register (EMACPC), Offset 0Xfc4
1582
Register 68: Ethernet MAC Clock Configuration Register (EMACCC), Offset 0Xfc8
1586
Register 69: Ethernet PHY Raw Interrupt Status (EPHYRIS), Offset 0Xfd0
1587
Register 70: Ethernet PHY Interrupt Mask (EPHYIM), Offset 0Xfd4
1588
Ethernet PHY Register Descriptions
1589
Register 72: Ethernet PHY Basic Mode Control - MR0 (EPHYBMCR), Address 0X000
1590
Register 73: Ethernet PHY Basic Mode Status - MR1 (EPHYBMSR), Address 0X001
1592
Register 74: Ethernet PHY Identifier Register 1 - MR2 (EPHYID1), Address 0X002
1595
Register 75: Ethernet PHY Identifier Register 2 - MR3 (EPHYID2), Address 0X003
1596
Register 76: Ethernet PHY Auto-Negotiation Advertisement - MR4 (EPHYANA), Address 0X004
1597
Register 77: Ethernet PHY Auto-Negotiation Link Partner Ability - MR5 (EPHYANLPA), Address 0X005
1599
Register 78: Ethernet PHY Auto-Negotiation Expansion - MR6 (EPHYANER), Address 0X006
1601
Register 79: Ethernet PHY Auto-Negotiation Next Page TX - MR7 (EPHYANNPTR), Address 0X007
1602
Register 80: Ethernet PHY Auto-Negotiation Link Partner Ability Next Page - MR8 (EPHYANLNPTR Address 0X008
1604
Register 81: Ethernet PHY Configuration 1 - MR9 (EPHYCFG1), Address 0X009
1606
Register 82: Ethernet PHY Configuration 2 - MR10 (EPHYCFG2), Address 0X00A
1609
Register 83: Ethernet PHY Configuration 3 - MR11 (EPHYCFG3), Address 0X00B
1611
Register 84: Ethernet PHY Register Control - MR13 (EPHYREGCTL), Address 0X00D
1613
Register 85: Ethernet PHY Address or Data - MR14 (EPHYADDAR), Address 0X00E
1615
Register 86: Ethernet PHY Status - MR16 (EPHYSTS), Address 0X010
1616
Register 87: Ethernet PHY Specific Control- MR17 (EPHYSCR), Address 0X011
1619
Register 88: Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1), Address 0X012
1622
Register 89: Ethernet PHY MII Interrupt Status 2 - MR19 (EPHYMISR2), Address 0X013
1625
Register 90: Ethernet PHY False Carrier Sense Counter - MR20 (EPHYFCSCR), Address 0X014
1628
Register 91: Ethernet PHY Receive Error Count - MR21 (EPHYRXERCNT), Address 0X015
1629
Register 92: Ethernet PHY bist Control - MR22 (EPHYBISTCR), Address 0X016
1630
Register 93: Ethernet PHY LED Control - MR24 (EPHYLEDCR), Address 0X018
1633
Register 94: Ethernet PHY Control - MR25 (EPHYCTL), Address 0X019
1634
Register 95: Ethernet PHY 10Base-T Status/Control - MR26 (EPHY10BTSC), Address 0X01A
1636
Register 96: Ethernet PHY bist Control and Status 1 - MR27 (EPHYBICSR1), Address 0X01B
1638
Register 97: Ethernet PHY bist Control and Status 2 - MR28 (EPHYBICSR2), Address 0X01C
1639
Register 98: Ethernet PHY Cable Diagnostic Control - MR30 (EPHYCDCR), Address 0X01E
1640
Register 99: Ethernet PHY Reset Control - MR31 (EPHYRCR), Address 0X01F
1641
Register 100: Ethernet PHY LED Configuration - MR37 (EPHYLEDCFG), Address 0X025
1642
Universal Serial Bus (USB) Controller
1644
Block Diagram
1645
Register Map
1646
Table 21-2. List of Registers
1647
Analog Comparators
1653
Block Diagram
1654
Functional Description
1655
Internal Reference Programming
1656
Initialization and Configuration
1658
Register Map
1659
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), Offset 0X000
1660
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), Offset 0X004
1661
Register 3: Analog Comparator Interrupt Enable (ACINTEN), Offset 0X008
1662
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), Offset 0X010
1663
Register 5: Analog Comparator Status 0 (ACSTAT0), Offset 0X020
1664
Register 8: Analog Comparator Control 0 (ACCTL0), Offset 0X024
1665
Register 11: Analog Comparator Peripheral Properties (ACMPPP), Offset 0Xfc0
1667
Pulse Width Modulator (PWM)
1669
Block Diagram
1670
Figure 23-1. PWM Module Diagram
1671
Signal Description
1672
PWM Comparators
1673
PWM Signal Generator
1674
Dead-Band Generator
1675
Synchronization Methods
1676
Fault Conditions
1677
Output Control Block
1678
Register Map
1679
Register Descriptions
1682
Register 1: PWM Master Control (PWMCTL), Offset 0X000
1683
Register 2: PWM Time Base Sync (PWMSYNC), Offset 0X004
1685
Register 3: PWM Output Enable (PWMENABLE), Offset 0X008
1686
Register 4: PWM Output Inversion (PWMINVERT), Offset 0X00C
1688
Register 5: PWM Output Fault (PWMFAULT), Offset 0X010
1690
Register 6: PWM Interrupt Enable (PWMINTEN), Offset 0X014
1692
Register 7: PWM Raw Interrupt Status (PWMRIS), Offset 0X018
1694
Register 8: PWM Interrupt Status and Clear (PWMISC), Offset 0X01C
1697
Register 9: PWM Status (PWMSTATUS), Offset 0X020
1700
Register 10: PWM Fault Condition Value (PWMFAULTVAL), Offset 0X024
1702
Register 11: PWM Enable Update (PWMENUPD), Offset 0X028
1704
Register 12: PWM0 Control (PWM0CTL), Offset 0X040
1708
Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), Offset 0X044
1713
Register 20: PWM0 Raw Interrupt Status (PWM0RIS), Offset 0X048
1716
Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), Offset 0X04C
1718
Register 28: PWM0 Load (PWM0LOAD), Offset 0X050
1720
Register 32: PWM0 Counter (PWM0COUNT), Offset 0X054
1721
Register 36: PWM0 Compare a (PWM0CMPA), Offset 0X058
1722
Register 40: PWM0 Compare B (PWM0CMPB), Offset 0X05C
1723
Register 44: PWM0 Generator a Control (PWM0GENA), Offset 0X060
1724
Register 48: PWM0 Generator B Control (PWM0GENB), Offset 0X064
1727
Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), Offset 0X06C
1731
Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), Offset 0X070
1732
Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), Offset 0X074
1733
Register 68: PWM0 Fault Source 1 (PWM0FLTSRC1), Offset 0X078
1735
Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), Offset 0X07C
1738
Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), Offset 0X800
1739
Register 84: PWM0 Fault Status 1 (PWM0FLTSTAT1), Offset 0X808
1742
Register 88: PWM Peripheral Properties (PWMPP), Offset 0Xfc0
1745
Register 89: PWM Clock Configuration (PWMCC), Offset 0Xfc8
1747
Quadrature Encoder Interface (QEI)
1748
Figure 24-1. QEI Block Diagram
1749
Signal Description
1750
Figure 24-3. Quadrature Encoder and Velocity Predivider Operation
1752
Initialization and Configuration
1753
Register Descriptions
1754
Register 1: QEI Control (QEICTL), Offset 0X000
1755
Register 2: QEI Status (QEISTAT), Offset 0X004
1758
Register 3: QEI Position (QEIPOS), Offset 0X008
1759
Register 4: QEI Maximum Position (QEIMAXPOS), Offset 0X00C
1760
Register 5: QEI Timer Load (QEILOAD), Offset 0X010
1761
Register 6: QEI Timer (QEITIME), Offset 0X014
1762
Register 7: QEI Velocity Counter (QEICOUNT), Offset 0X018
1763
Register 8: QEI Velocity (QEISPEED), Offset 0X01C
1764
Register 9: QEI Interrupt Enable (QEIINTEN), Offset 0X020
1765
Register 10: QEI Raw Interrupt Status (QEIRIS), Offset 0X024
1767
Register 11: QEI Interrupt Status and Clear (QEIISC), Offset 0X028
1769
Pin Diagram
1771
Signal Tables
1772
Signals by Pin Number
1773
Signals by Signal Name
1785
Signals by Function, Except for GPIO
1797
GPIO Pins and Alternate Functions
1808
Possible Pin Assignments for Alternate Functions
1811
Connections for Unused Signals
1816
Electrical Characteristics
1818
Operating Characteristics
1819
Recommended Operating Conditions
1820
Table 27-8. Recommended Slow GPIO Pad Operating Conditions
1821
Table 27-10. Maximum GPIO Package Side Assignments
1822
Load Conditions
1823
JTAG and Boundary Scan
1824
Figure 27-2. JTAG Test Clock Input Timing
1825
Power and Brown-Out
1826
Response
1829
Reset
1831
Figure 27-10. Brown-Out Reset Timing
1832
Figure 27-14. MOSC Failure Reset Timing
1833
On-Chip Low Drop-Out (LDO) Regulator
1834
Clocks
1835
Table 27-18. Actual PLL Frequency
1836
PIOSC Specifications
1837
Main Oscillator Specifications
1838
Table 27-24. Crystal Parameters
1840
System Clock Specification with ADC Operation
1842
Sleep Modes
1843
Hibernation Module
1845
Figure 27-15. Hibernation Module Timing
1846
Flash Memory
1847
Eeprom
1848
Input/Output Pin Characteristics
1849
Table 27-35. Slow GPIO Module Characteristics
1850
Types of I/O Pins and ESD Protection
1851
Figure 27-17. ESD Protection for Non-Power Pins (Except WAKE Signal)
1852
External Peripheral Interface (EPI)
1853
Figure 27-18. SDRAM Initialization and Load Mode Register Timing
1854
Figure 27-20. SDRAM Write Timing
1855
Figure 27-21. Host-Bus 8/16 Asynchronous Mode Read Timing
1856
Figure 27-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing
1857
Figure 27-25. General-Purpose Mode Read and Write Timing
1858
Figure 27-26. PSRAM Single Burst Read
1859
Figure 27-27. PSRAM Single Burst Write
1860
Analog-To-Digital Converter (ADC)
1861
Table 27-45. ADC Electrical Characteristics for ADC at 2 Msps
1863
Figure 27-28. ADC External Reference Filtering
1866
Synchronous Serial Interface (SSI)
1867
Measurement
1868
Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1
1869
Ethernet Controller
1871
AC Characteristics
1872
Figure 27-37. 100 Base-TX Transmit Timing
1873
Figure 27-39. Auto-Negotiation Fast Link Pulse Timing
1874
Universal Serial Bus (USB) Controller
1875
Figure 27-41. ULPI Interface Timing Diagram
1876
Analog Comparator
1877
Pulse-Width Modulator (PWM)
1879
Current Consumption
1880
Table 27-64. Peripheral Current Consumption
1884
A Package Information
1885
A.4 Packaging Diagram
1887
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