Page 1 CC3200 SimpleLink Wi-Fi and Internet-of- Things Solution, a Single Chip Wireless MCU Technical Reference Manual Literature Number: SWRU367D June 2014 – Revised May 2018...
Page 2: Table Of Contents
Overview ..................... Functional Description ..................3.2.1 System Timer (SysTick) ..............3.2.2 Nested Vectored Interrupt Controller (NVIC) ..................3.2.3 System Control Block (SCB) Contents SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 3 7.2.6 Command Sequence Flow Charts ................. 7.2.7 Initialization and Configuration ......................Register Map ..................... 7.3.1 I2C Registers ..................SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Contents Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 4 SD Host Features ......................11.3 1-Bit SD Interface ................11.3.1 Clock and Reset Management ............... 11.4 Initialization and Configuration Using Peripheral APIs Contents SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 5 14.4.1 Camera Core Reset ................14.4.2 Enable the Picture Acquisition ................14.4.3 Disable the Picture Acquisition ......................14.5 Interrupt Handling ................14.5.1 FIFO_OF_IRQ (FIFO overflow) SWRU367D – June 2014 – Revised May 2018 Contents Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 6 16.8.3 Control Architecture ................... 16.8.4 CC3200 Pin-mux Examples ....................16.8.5 Wake on Pad ....................16.8.6 Sense on Power ................... Software Development Kit Examples Contents SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 7: Contents
B.1.6 DMA_RIS Register (offset = A4h) [reset = 0h] ............B.1.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h] ........................Revision History SWRU367D – June 2014 – Revised May 2018 Contents Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 8 Cortex-M4 Register Set ........................ 2-4. Data Storage ........................ 2-5. Vector Table ....................2-6. Exception Stack Frame ..............2-7. Power Management Architecture in CC3200 SoC ......................3-1. ACTLR Register ......................3-2. STCTRL Register ...................... 3-3. STRELOAD Register ....................3-4. STCURRENT Register ....................
Page 9 7-6. Data Validity During Bit Transfer on the I2C Bus ....................7-7. Master Single TRANSMIT ....................7-8. Master Single RECEIVE SWRU367D – June 2014 – Revised May 2018 List of Figures Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 10 8-16. Flow Chart - FIFO Mode Common Sequence (Master) ........8-17. Flow Chart - FIFO Mode Transmit and Receive with Word Count (Master) List of Figures SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 11 10-9. WatchDog Flow Chart ................10-10. System WatchDog Recovery Sequence ................11-1. SDHost Controller Interface Block Diagram ....................11-2. MMCHS_CSRE Register SWRU367D – June 2014 – Revised May 2018 List of Figures Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 12 11-17. MMCHS_ISE Register ........................ 12-1. I2S Protocol ......................12-2. MCASP Module ......................12-3. Logical Clock Path ................13-1. Architecture of the ADC Module in CC3200 ....................13-2. Operation of the ADC ..................... 13-3. ADC_CTRL Register ................... 13-4. ADC_CH0_IRQ_EN Register ...................
Page 13 14-15. CC_CTRL_XCLK Register ....................14-16. CC_FIFODATA Register ............ 15-1. Power Management Unit Supports Two Supply Configurations ......................15-2. Sleep Modes ..............15-3. Power Management Control Architecture in CC3200 ....................15-4. CAMCLKCFG Register ....................15-5. CAMCLKEN Register ....................15-6. CAMSWRST Register ....................
Page 14 16-1. Board Configuration to Use Pins 45 and 52 as Digital Signals ............. 16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals ............. 16-3. I/O Pad Data and Control Path Architecture in CC3200 ..................16-4. Wake on Pad for Hibernate Mode .......................
Page 15 DMA_SRCENDP Register Field Descriptions ................. 4-7. DMA_DSTENDP Register Field Descriptions ................4-8. DMA_CHCTL Register Field Descriptions ............4-9. DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers SWRU367D – June 2014 – Revised May 2018 List of Tables Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 16 UARTLCRH Register Field Descriptions ................. 6-10. UARTCTL Register Field Descriptions ................6-11. UARTIFLS Register Field Descriptions ................... 6-12. UARTIM Register Field Descriptions List of Tables SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 17 8-12. SPI_CHCONF Register Field Descriptions ................8-13. SPI_CHSTAT Register Field Descriptions ................8-14. SPI_CHCTRL Register Field Descriptions ..................8-15. SPI_TX Register Field Descriptions SWRU367D – June 2014 – Revised May 2018 List of Tables Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 18 11-6. MMCHS_CON Register Field Descriptions ................11-7. MMCHS_BLK Register Field Descriptions ................11-8. MMCHS_ARG Register Field Descriptions ................11-9. MMCHS_CMD Register Field Descriptions List of Tables SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 19 14-8. CC_CTRL Register Field Descriptions ................. 14-9. CC_CTRL_DMA Register Field Descriptions ................ 14-10. CC_CTRL_XCLK Register Field Descriptions ................14-11. CC_FIFODATA Register Field Descriptions SWRU367D – June 2014 – Revised May 2018 List of Tables Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 20 15-46. TURBOREQ Register Field Descriptions ................ 15-47. DSLPWAKECFG Register Field Descriptions ................15-48. DSLPTIMRCFG Register Field Descriptions ................15-49. SLPWAKEEN Register Field Descriptions List of Tables SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 21 DMA_ICR Register Field Descriptions ................. B-6. DMA_MIS Register Field Descriptions ................. B-7. DMA_RIS Register Field Descriptions ................B-8. GPTTRIGSEL Register Field Descriptions SWRU367D – June 2014 – Revised May 2018 List of Tables Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 22: Architecture Overview
SWRU367D – June 2014 – Revised May 2018 Architecture Overview ........................... Topic Page ....................... Introduction ..................Architecture Overview ................... Functional Overview Architecture Overview SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 23: Introduction
Introduction Created for the Internet of Things (IoT), the SimpleLink CC3200 device is a wireless MCU that integrates a high-performance ARM Cortex-M4 MCU, allowing customers to develop an entire application with a single IC. With on-chip Wi-Fi, Internet, and robust security protocols, no prior Wi-Fi experience is required for faster development.
Page 24: Architecture Overview
Architecture Overview www.ti.com Architecture Overview The building blocks of CC3200 system-on-chip are shown in Figure 1-1 Figure 1-1. CC3200 MCU and WIFI System-on-Chip Architecture Overview SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 25: Functional Overview
Functional Overview www.ti.com Functional Overview The following sections provide an overview of the main components of the CC3200 system on chip (SoC) from a microcontroller point of view. 1.3.1 Processor Core 1.3.1.1 ARM Cortex M4 Processor Core The CC3200 application MCU subsystem is built around an ARM Cortex-M4 processor core, which provides outstanding computational performance and exceptional system response to interrupts at low power consumption while optimizing memory footprint –...
Page 26: 1.3.2 Memory
1.3.1.3 Nested Vector Interrupt Controller (NVIC) CC3200 includes the ARM NVIC. The NVIC and Cortex-M3 prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to the state saving, thus enabling efficient interrupt entry.
Page 27: Micro Direct Memory Access Controller (Μdma)
Functional Overview www.ti.com The CC3200 DriverLib is a software library that controls on-chip peripherals. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. The ROM DriverLib provides a rich set of drivers for peripheral and chip. It is aimed at reducing application development time and improving solution robustness.
Page 28: Watch Dog Timer (Wdt)
1.3.5 Watch Dog Timer (WDT) The watchdog timer in the CC3200 restarts the system when it gets stuck due to an error and does not respond as expected. The watchdog timer can be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second time-out.
Page 29: Inter-Integrated Circuit Interface (I2C)
SDA and a serial clock line SCL). The I2C bus interfaces to a wide variety of external I2C devices such as sensors, serial memory, control ports of image sensors, and audio codecs. Multiple slave devices can be connected to the same I2C bus. The CC3200 microcontroller includes one I2C module with the following features: •...
Page 30: General Purpose Input / Output (Gpio)
1.3.10 General Purpose Input / Output (GPIO) All digital pins of the CC3200 device and some of the analog pins can be used as a general-purpose input/output (GPIO). The GPIOs are grouped as 4 instance GPIO modules, each 8-bit. Supported features include: •...
Page 31: 1.3.15 Hardware Cryptography Accelerator
1.3.15 Hardware Cryptography Accelerator The secure variant of the CC3200 includes a suite of high-throughput, state-of-the-art hardware accelerators for fast computation of ciphers (AES, DES, 3-DES), hashing (SHA, MD5), and CRC algorithms by the application. It is also referred as the data hashing and transform engine (DTHE). Further details about the hardware cryptography accelerator will be addressed in the revision of this manual.
Page 32: 1.3.17 Simplelink Subsystem
The SimpleLink subsystem provides fast, secured WLAN and Internet connections with 256-bit encryption. The CC3200 device supports station, AP, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi network processor includes an embedded IPv4 TCP/IP stack.
Page 33: Cortex-M4 Processor
Chapter 2 SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor ........................... Topic Page ......................Overview ..................Functional Description SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 34: Overview
• Low-power consumption with multiple sleep modes The ARM Cortex-M4 application processor core in the CC3200 does not include the floating point unit and memory protection unit (FPU and MPU). This chapter provides information on the implementation of the Cortex-M4 application processor in the CC3200, including the programming model, the memory model, the exception model, fault handling, and power management.
Page 35: 2.1.2 System-Level Interface
See the ARM Debug Interface V5 Architecture Specification for details on SWJ-DP. The 4-bit trace interface from embedded trace macrocell (ETM) is not supported in the CC3200 due to pin limitations. Instead, the processor integrates an instrumentation trace macrocell (ITM) alongside data watchpoints and a profiling unit.
Page 36: Trace Port Interface Unit (Tpiu)
– Limited access to the MSR and MRS instructions, and no use of the CPS instruction – No access to the system timer, NVIC, or system control block Cortex-M4 Processor SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 37: Register Description
The core registers are not memory-mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 38: Cortex-M4 Register Set
Program Status Register PRIMASK 0x0000.0000 Priority Mask Register FAULTMASK 0x0000.0000 Fault Mask Register BASEPRI 0x0000.0000 Base Priority Mask Register CONTROL 0x0000.0000 Control Register Cortex-M4 Processor SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 39 Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 40: Psr Register Combinations
ARM Cortex-M4 Devices Generic User Guide (ARM DUI 0553A), or perform an exception return to thread mode with the appropriate EXC_RETURN value. Cortex-M4 Processor SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 41: Memory Model
0553A). 2.2.2.1.3 Exceptions and Interrupts The Cortex-M4 application processor in the CC3200 supports interrupts and system exceptions. The processor and the nested vectored interrupt controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset.
Page 42: Sram Memory Bit-Banding Regions
This allows bit-band accesses to match the access requirements of the underlying peripheral. The CC3200 family of Wi-Fi microcontrollers support up to 256 Kbyte of on-chip SRAM for code and data. The SRAM starts from address 0x2000 0000.
Page 43: Data Storage
• The word instructions LDREX and STREX • The halfword instructions LDREXH and STREXH • The byte instructions LDREXB and STREXB SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 44: Exception Model
0553A). 2.2.4 Exception Model The ARM Cortex-M4 application processor in the CC3200 and the nested vectored interrupt controller (NVIC) prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (ISR).
Page 45 NMI is permanently enabled and has a fixed priority of –2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. NMI in the CC3200 is reserved for the internal system, and is not available for application usage. •...
Page 46: Exception Types
In the system, peripherals use interrupts to communicate with the processor. Table 2-5 lists the interrupts on the CC3200 application processor For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler.
Page 47 Functional Description www.ti.com Table 2-7. CC3200 Application Processor Interrupts (continued) Interrupt Number (Bit in Interrupt Vector Adderess or Offset Description Type Registers) 0x0000.0084 ADC Channel-3 0x0000.0088 0x0000.008C 16/32-Bit Timer A0A 0x0000.0090 16/32-Bit Timer A0B 0x0000.0094 16/32-Bit Timer A1A 0x0000.0098 16/32-Bit Timer A1B 0x0000.009C...
Page 48: Vector Table
0. NOTE: Configurable priority values for the CC3200 implementation are in the range 0-7. This means that the reset, hard fault, and NMI exceptions (NMI is reserved for use by the system) with fixed negative priority values always have higher priority than any other exception.
Page 49 Figure 2-6 shows the Cortex-M4 stack frame layout, which is similar to that of ARMv7-M implementations without an FPU. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 50: Fault Handling
Default memory mismatch on Memory management fault Memory Management Fault MSTKE exception stacking Status (MFAULTSTAT) Occurs on an access to an XN region. Cortex-M4 Processor SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 51 NOTE: Only reset and NMI can preempt the fixed-priority hard fault. A hard fault can preempt any exception other than reset, NMI, or another hard fault. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 52: Power Management
NMI occurs, or it is halted by a debugger. 2.2.6 Power Management The CC3200 Wi-Fi microcontroller is a multi-processor system-on-chip. An advanced power management scheme has been implemented at chip level that delivers the best-in-class energy efficiency across a wide class of application profiles, while handling the asynchronous sleep-wake requirements of multiple high performance processors and Wi-Fi radio subsystems.
Page 53: Power Management Architecture In Cc3200 Soc
Functional Description www.ti.com Figure 2-7 shows the architecture of the CC3200 SoC level power management, especially from the application point of view. Figure 2-7. Power Management Architecture in CC3200 SoC The Cortex-M4 processor implementation inside the CC3200 multiprocessor SoC has a few differences when compared to a discrete MCU.
Page 54: Instruction Set Summary
RUN (or ACTIVE) state should then be minimized. The dedicated Cortex-M4 application processor in CC3200 is particularly suited for this mode of operation due to its advanced power management, DMA, zero wait state multi-layer AHB interconnect, fast execution and retention over the entire range of zero- wait state SRAM.
Page 55 Saturating add and subtract with exchange QDADD {Rd,} Rn, Rm Saturating double and add QDSUB {Rd,} Rn, Rm Saturating double and subtract SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 56 SMMUL, SMMULR {Rd,} Rn, Rm Signed most significant word multiply SMUAD SMUADX {Rd,} Rn, Rm Signed dual multiply add Cortex-M4 Processor SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 57 Unsigned add and subtract with exchange UHADD16 {Rd,} Rn, Rm Unsigned halving add 16 UHADD8 {Rd,} Rn, Rm Unsigned halving add 8 SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Processor Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 58 {Rd,} Rm, {,ROR #n} Unsigned Extend Byte 16 UXTH {Rd,} Rm, {,ROR #n} Zero extend a Halfword Wait for event Wait for interrupt Cortex-M4 Processor SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 59: Cortex-M4 Peripherals
SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals ........................... Topic Page ......................Overview ..................Functional Description ..................... Register Map SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 60: Overview
Overview www.ti.com Overview This chapter provides information on the CC3200 implementation of the Cortex-M4 application processor in CC3200 peripherals, including: • SysTick (see Section 3.2.1) – Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. •...
Page 61: Nested Vectored Interrupt Controller (Nvic)
In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 62: System Control Block (Scb)
0x184 DIS1 0x0000.0000 Interrupt 32-63 Clear Enable 0x188 DIS2 0x0000.0000 Interrupt 64-95 Clear Enable 0x18C DIS3 0x0000.0000 Interrupt 96-127 Clear Enable Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 63 Interrupt 20-23 Priority 0x418 PRI6 0x0000.0000 Interrupt 24-27 Priority 0x41C PRI7 0x0000.0000 Interrupt 28-31 Priority 0x420 PRI8 0x0000.0000 Interrupt 32-35 Priority SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 64 Interrupt 156-159 Priority 0x4A0 PRI40 0x0000.0000 Interrupt 160-163 Priority 0x4A4 PRI41 0x0000.0000 Interrupt 164-167 Priority 0x4A8 PRI42 0x0000.0000 Interrupt 168-171 Priority Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 65 Configurable Fault Status 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 0xD34 MMADDR Memory Management Fault Address 0xD38 FAULTADDR Bus Fault Address SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 66: Peripheral Registers
D2Ch HFAULTSTAT Hard Fault Status Section 3.3.1.22 D38h FAULTDDR Bus Fault Address Section 3.3.1.23 F00h SWTRIG Software Trigger Interrupt Section 3.3.1.24 Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 67: Actlr Register
IT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 application processor in CC3200 and does not normally require modification. Figure 3-1. ACTLR Register...
Page 68: Stctrl Register
0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 69: Streload Register
31-24 RESERVED 23-0 RELOAD Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 70: Stcurrent Register
Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 71: En_0 To En_6 Register
0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, enables the interrupt. 1h (R) = On a read, indicates the interrupt is enabled. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 72: Dis_0 To Dis_6 Register
0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, no effect. 1h (R) = On a read, indicates the interrupt is enabled. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 73: Pend_0 To Pend_6 Register
1h (W) = On a write, the corresponding interrupt is set to pending even if it is disabled. 1h (R) = On a read, indicates that the interrupt is pending. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 74: Unpend_0 To Unpend_6 Register
UNPEND6) register so that interrupt [n] is no longer pending. 1h (R) = On a read, indicates that the interrupt is pending. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 75: Active_0 To Active_6 Register
Interrupt Active 0h = The corresponding interrupt is not active. 1h = The corresponding interrupt is active, or active and pending. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 76: Pri_0 To Pri_49 Register
Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 77: Cpuid Register
Constant Value Description 0xF Always reads as 0xF. 15-4 PARTNO C24h Part Number C24h = Cortex-M4 application processor in CC3200. Revision Number 1h = The pn value in the rnpn product revision identifier, for example, the 1 in r0p1. SWRU367D – June 2014 – Revised May 2018...
Page 78: Intctrl Register
1h (W) = On a write, changes the SysTick exception state to pending. 1h (R) = On a read, indicates a SysTick exception is pending. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 79 Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 80: Vtable Register
Because there are 199 interrupts, the offset must be aligned on a 1024-byte boundary. RESERVED Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 81: Apint Register
0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. ENDIANESS Data Endianess The CC3200 implementation uses only little-endian mode so this is cleared to 0. 14-11 RESERVED...
Page 82: Sysctrl Register
1h = When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. RESERVED Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 83: Cfgctrl Register
0h = Do not trap on unaligned halfword and word accesses. 1h = Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 84 0h = The processor can enter Thread mode only when no exception is active. 1h = The processor can enter Thread mode from any level under the control of an EXC_RETURN value. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 85: Syspri1 Register
Configurable priority values are in the range 0-7, with lower values having higher priority. RESERVED SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 86: Syspri2 Register
SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 28-0 RESERVED Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 87: Syspri3 Register
Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. RESERVED SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 88: Syshndctrl Register
0h = A bus fault exception is not pending. 1h = A bus fault exception is pending. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 89 Caution above before setting this bit. 0h = Memory management fault is not active. 1h = Memory management fault is active. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 90: Faultstat Register
Usage Fault Status (UFAULTSTAT), bits 31:16 Bus Fault Status (BFAULTSTAT), bits 15:8 Memory Management Fault Status (MFAULTSTAT), bits 7:0 (Not applicable for CC3200) FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: The...
Page 91 0h = No bus fault has occurred on unstacking for a return from exception. 1h = Unstacking for a return from exception has caused one or more bus faults. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 92 0h = No memory management fault has occurred on unstacking for a return from exception. 1h = Unstacking for a return from exception has caused one or more access violations. RESERVED Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 93 0h = An instruction access violation has not occurred. 1h = The processor attempted an instruction fetch from a location that does not permit execution. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 94: Hfaultstat Register
0h = No bus fault has occurred on a vector table read. 1h = A bus fault occurred on a vector table read. RESERVED Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 95: Faultddr Register
Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. SWRU367D – June 2014 – Revised May 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 96: Swtrig Register
Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. Cortex-M4 Peripherals SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 97: Direct Memory Access (Dma)
SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) ........................... Topic Page ......................Overview ..................Functional Description ..................Register Description SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 98: Overview
Overview The CC3200 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M4 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals.
Page 99: Dma Channel Assignment
Peripherals are mapped at multiple places to address the application need where any combination of peripheral can be used in tandem. Figure 4-1. DMA Channel Assignment SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 100: Priority
Channel 1 – primary …. 0x1F0 Channel 31 – primary 0x200 Channel 0 – alternate 0x210 Channel 1 – alternate …. Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 101: Transfer Mode
Generally, auto mode is not used with a peripheral. When all the items have been transferred using auto mode, the μDMA controller sets the mode for that channel to stop. SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 102 Data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 103: Ping-Pong Mode
Functional Description www.ti.com Figure 4-2. Ping-Pong Mode SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 104 The primary control structure for the channel used for the operation is configured to copy from the task list to the alternate control structure. Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 105: Memory Scatter-Gather Mode
By using this method, the μDMA controller can transfer data to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 106: Peripheral Scatter-Gather Mode
Destination address increment Byte Source end pointer Peripheral FIFO register Destination end pointer End of data buffer in memory Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 107: Peripheral Interface
The ERRCLR bit is set if an error occurred. The error can be cleared by writing a 1 to the ERRCLR bit. SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 108: Register Description
0x038 DMA_PRIOSET 0x0000.0000 DMA Channel Priority 0x03C DMA_PRIOCLR DMA Channel Priority Clear 0x04C DMA_ERRCLR 0x0000.0000 DMA Bus Error Clear Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 109: Μdma Channel Control Structure
0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 110: Dma Registers
DMA Channel Source Address End Pointer Section 4.3.3.1 DMA_DSTENDP DMA Channel Destination Address End Pointer Section 4.3.3.2 DMA_CHCTL DMA Channel Control Word Section 4.3.3.3 Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 111: Dma_Srcendp Register
DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 112: Dma_Dstendp Register
DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 113: Dma_Chctl Register
3h = No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel 23-18 RESERVED SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 114 4h = Memory Scatter-Gather 5h = Alternate memory scatter gather 6h = Peripheral scatter gather 7h = Alternate peripheral scatter gather Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 115: Dma_(Offset_From_Dma_Base_Address) Registers
DMA Channel Map Select 2 Section 4.3.4.21 51Ch DMA_CHMAP3 DMA Channel Map Select 3 Section 4.3.4.22 FB0h DMA_PV DMA Peripheral Version Section 4.3.4.23 SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 116: Dma_Stat Register
9h = Done RESERVED MASTEN Master enable status. 0h = DMA controller is disabled 1h = DMA controller is enabled Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 117: Dma_Cfg Register
Type Reset Description 31-1 RESERVED MASTEN Controller Master enable 0h = Disables DMA controller 1h = Enables DMA controller SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 118: Dma_Ctlbase Register
This field contains the pointer to the base address of the channel control table. The base address must be 1024-byte aligned. RESERVED Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 119: Dma_Altbase Register
Reset Description 31-0 ADDR Alternate Channel Address. This field provides the base address of the alternate channel control structures SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 120: Dma_Waitstat Register
0h = The corresponding channel is not waiting on a request. 1h = The corresponding channel is waiting on a request. Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 121: Dma_Swreq Register
These bits are automatically cleared when the software request has been completed. 0h = No request generated 1h = Generate a software request for the corresponding channel. SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 122: Dma_Useburstset Register
0h = DMA channel [n] responds to single or burst requests. 1h = DMA channel [n] responds only to burst requests Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 123: Dma_Useburstclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that DMA channel [n] responds to single and burst requests SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 124: Dma_Reqmaskset Register
1h = The peripheral associated with channel [n] is not able to request DMA transfers. Channel [n] may be used for software- initiated transfers. Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 125: Dma_Reqmaskclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that the peripheral associated with channel [n] is enabled to request DMA transfers. SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 126: Dma_Enaset Register
DMAENACLR register or when the end of a DMA transfer occurs. 0h = DMA Channel [n] is disabled. 1h = DMA Channel [n] is enabled. Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 127: Dma_Enaclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel [n] is disabled for DMA transfers SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 128: Dma_Altset Register
0h = DMA channel [n] is using the primary control structure 1h = DMA channel [n] is using the alternate control structure Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 129: Dma_Altclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel [n] is using the primary control structure SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 130: Dma_Prioset Register
0h = DMA channel [n] is using the default priority level 1h = DMA channel [n] is using the high priority level Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 131: Dma_Prioclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that channel [n] is using the default priority level SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 132: Dma_Errclr Register
R/W1C DMA Bus Error Status 0h = No bus error is pending. 1h = A bus error is pending. Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 133: Dma_Chasgn Register
CHASGN_n Channel [n] Assignment Select 0h = Use the primary channel assignment. 1h = Use the secondary channel assignment. SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 134: Dma_Chmap0 Register
11-8 CH2SEL_n DMA channel 2 source select CH1SEL_n DMA channel 1 source select CH0SEL_n DMA channel 0 source select Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 135: Dma_Chmap1 Register
11-8 CH10SEL_n DMA channel 10 source select CH9SEL_n DMA channel 9 source select CH8SEL_n DMA channel 8 source select SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 136: Dma_Chmap2 Register
11-8 CH18SEL_n DMA channel 18 source select CH17SEL_n DMA channel 17 source select CH16SEL_n DMA channel 16 source select Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 137: Dma_Chmap3 Register
11-8 CH26SEL_n DMA channel 26 source select CH25SEL_n DMA channel 25 source select CH24SEL_n DMA channel 24 source select SWRU367D – June 2014 – Revised May 2018 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 138: Dma_Pv Register
Table 4-32. DMA_PV Register Field Descriptions Field Type Reset Description 31-16 RESERVED 15-8 MAJVER Major Version MINVER Minor Version Direct Memory Access (DMA) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 139: General-Purpose Input/Outputs (Gpios)
General-Purpose Input/Outputs (GPIOs) ........................... Topic Page ......................Overview ..................Functional Description ....................Interrupt Control ................Initialization and Configuration ............... GPIO_REGISTER_MAP Registers SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 140: Digital I/O Pads
Overview This chapter describes the general purpose input/output module and the I/O pad cells in the CC3200. The GPIO module is composed of 4 physical GPIO blocks, each corresponding to an individual GPIO port (Port 0, Port A1, Port A2, Port A3). The GPIO module supports up to 32 programmable input/output pins when GPIO function is selected in I/O pin muxing.
Page 141: Gpiodata Write Example
GPIODATA bits 5, 4, and 0 with a single operation by using GPIODATA address alias 0x0C4 (offset address with regard to the base of the respective GPIO instance S0 to S4). Figure 5-3. GPIODATA Read Example SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 142: Interrupt Control
Unmask the port by setting the IME field in the GPIOIM register. Table 5-1. GPIO Pad Configuration Examples GPIO Register Bit Value Configuration Digital Input (GPIO) General-Purpose Input/Outputs (GPIOs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 143: Gpio Interrupt Configuration Example
0=single edge GPIOIBE 1=both edges 0=Low level, or falling edge GPIOIEV 1=High level, or rising edge 0=masked GPIOIM 1=not masked SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 144: Gpio_Register_Map Registers
GPIO Interrupt Clear Section 5.5.1.9 5.5.1 GPIO Register Description The remainder of this section lists and describes the GPIO registers. General-Purpose Input/Outputs (GPIOs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 145: Gpiodata Register
Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 146: Gpiodir Register
Description 31-8 RESERVED GPIO Data Direction 0h = Corresponding pin is an input. 1h = Corresponding pins is an output. General-Purpose Input/Outputs (GPIOs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 147: Gpiois Register
0h = The edge on the corresponding pin is detected (edge- sensitive). 1h = The level on the corresponding pin is detected (level-sensitive). SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 148: Gpioibe Register
0h = Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register. 1h = Both edges on the corresponding pin trigger an interrupt. General-Purpose Input/Outputs (GPIOs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 149: Gpioiev Register
0h = A falling edge or a Low level on the corresponding pin triggers an interrupt. 1h = A rising edge or a High level on the corresponding pin triggers an interrupt. SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 150: Gpioim Register
0h = The interrupt from the corresponding pin is masked. 1h = The interrupt from the corresponding pin is sent to the interrupt controller. General-Purpose Input/Outputs (GPIOs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 151: Gpioris Register
0h = An interrupt condition has not occurred on the corresponding pin. 1h = An interrupt condition has occurred on the corresponding pin. SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 152: Gpiomis Register
1h = An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. General-Purpose Input/Outputs (GPIOs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 153: Gpioicr Register
Description 31-8 RESERVED GPIO Interrupt Clear 0h = The corresponding interrupt is unaffected. 1h = The corresponding interrupt is cleared. SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 154: Gpio_Trig_En Register Field Descriptions
GPIOA3 GPIO_25 GPIO_26 (Restricted Use; Antenna GPIOA3 Selection 1 Only) GPIO_27 (Restricted Use; Antenna GPIOA3 Selection 2 Only) GPIOA3 GPIO_28 General-Purpose Input/Outputs (GPIOs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 155 Table 5-14. GPIO Mapping (continued) GPIO Module Instance GPIO Bit GPIO # GPIOA3 GPIO_29 GPIOA3 GPIO_30 (PM/Dig Mux) GPIOA3 GPIO_31 (PM/Dig Mux) SWRU367D – June 2014 – Revised May 2018 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 156: Universal Asynchronous Receivers/Transmitters (Uarts)
SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... Topic Page ......................Overview ..................Functional Description ..................Register Description Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 157: Overview
Overview www.ti.com Overview The CC3200 includes two Universal Asynchronous Receivers/Transmitters (UART) with the following features: • Programmable baud-rate generator allowing speeds up to 3 Mbps. • Separate 16×8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading •...
Page 158: Uart Module Block Diagram
Figure 6-1. UART Module Block Diagram Functional Description Each CC3200 UART performs the functions of parallel-to-serial and serial-to-parallel conversions. The UART is configured for transmit and receive through the TXE and RXE bits of the UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in the UARTCTL register.
Page 159: Uart Character Frame
Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 160: Flow Control Mode
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 161 TXRIS bit is set. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 162: Initialization And Configuration
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 163: Register Description
0x040 UARTMIS 0x0000.0000 UART Masked Interrupt Status 0x044 UARTICR 0x0000.0000 UART Interrupt Clear 0x048 UARTDMACTL 0x0000.0000 UART DMA Control SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 164: Uart Registers
UARTMIS UART Masked Interrupt Status Section 6.3.1.11 UARTICR UART Interrupt Clear Section 6.3.1.12 UARTDMACTL UART DMA Control Section 6.3.1.13 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 165: Uartdr Register
UART is written to this field. When read, this field contains the data that was received by the UART. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 166: Uartrsr_Uartecr Register
FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 167 This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 168: Uartfr Register
1h = If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 169 1h = The U1CTS signal is asserted. This bit is implemented only on UART1 and is reserved for UART0 SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 170: Uartibrd Register Field Descriptions
UARTLCRH register. Table 6-7. UARTIBRD Register Field Descriptions Field Type Reset Description 31-16 RESERVED 15-0 DIVINT Integer Baud-Rate Divisor Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 171: Uartfbrd Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-8. UARTFBRD Register Field Descriptions Field Type Reset Description 31-6 RESERVED DIVFRAC Fractional Baud-Rate Divisor SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 172: Uartlcrh Register
When in 7816 smartcard mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 173 For the proper execution of the break command, software must set this bit for at least two frames (character periods). SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 174: Uartctl Register
U1RTS signal. If RTSEN is set, this bit is ignored on a write and should be ignored on read. Reserved Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 175 If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 176: Uartifls Register
FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 177: Uartim Register
1h = An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 178 1h = An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set. RIIM Reserved Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 179: Uartris Register
1h = A break error has occurred. This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 180 1h = Clear to Send used for software flow control. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. RIRIS Reserved Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 181: Uartmis Register
1h = An unmasked interrupt was signaled due to a break error. This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 182 1h = An unmasked interrupt was signaled due to Clear to Send. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. RIMIS Reserved Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 183: Uarticr Register
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 184 Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register and the CTSMIS bit in the UARTMIS register. RIMIC Reserved Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 185: Uartdmactl Register
Receive DMA Enable 0h = DMA for the receive FIFO is disabled. 1h = DMA for the receive FIFO is enabled. SWRU367D – June 2014 – Revised May 2018 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 186: Inter-Integrated Circuit (I2C) Interface
SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface ........................... Topic Page ......................Overview ..................Functional Description ....................Register Map Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 187: Overview
– Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 188: I2C Block Diagram
The CONFMODE bits in the GPIO_PAD_CONFIG register should be set to choose the I2C function. Set the I2CSDA and I2CSCL pins to open-drain using the IODEN bits of the GPIO_PAD_CONFIG register. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 189: I2C Bus Configuration
Pin R Functional Description The CC3200 has one instance of an I2C module comprised of both master and slave functions, identified by a unique address. A master-initiated communication generates the clock signal, SCL. For proper operation, the SDA and SCL pin must be configured as an open-drain signal. Both SDA and SCL signals must be connected to a positive supply voltage using a pullup resistor.
Page 190: Start And Stop Conditions
The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 7-6). Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 191: Data Validity During Bit Transfer On The I2C Bus
4. The master does not generate a STOP condition, but instead writes another slave address to the I2CMSA register, then writes 0x3 to initiate the repeated START. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 192 The OAR2SEL bit in the I2CSCSR register indicates if the ACKed address is the alternate address or not. When this bit is clear, it indicates either legacy operation or no address match. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 193: Supported Speed Modes
BURST transaction initiated. 7.2.2 Supported Speed Modes The I2C bus in the CC3200 can run in standard mode (100 kbps) or fast mode (400 kbps). The selected mode should match the speed of the other I2C devices on the bus.
Page 194: Interrupts
The transmit FIFO can be assigned to the master, while the receive FIFO is assigned to the slave, and Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 195 TX FIFO fill level is less than the trigger set). If the I2CMBLEN register value is less than 4 and the TX FIFO is not full but more than trigger level, only dma_sreq asserts. Single requests are generated SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 196: Command Sequence Flow Charts
7.2.6.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 197: Master Single Transmit
I2CMDR Read I2CMCS BUSBSY bit=0? Write ---0-111 to I2CMCS Read I2CMCS BUSY bit=0? Error Service ERROR bit=0? Idle SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 198: Master Single Receive
BUSBSY bit=0? Write ---00111 to I2CMCS Read I2CMCS BUSY bit=0? Error Service ERROR bit=0? Read data from I2CMDR Idle Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 199: Master Transmit Of Multiple Data Bytes
Index=n? to I2CMCS Error Service Write ---0-101 to I2CMCS Idle Read I2CMCS BUSY bit=0? Error Service ERROR bit=0? Idle SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 200: Master Receive Of Multiple Data Bytes
Error Service Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? ERROR bit=0? Read data from Error Service I2CMDR Idle Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 201: Master Receive With Repeated Start After Master Transmit
Write ---01011 to I2CMCS Repeated START condition is generated with changing data Master operates in direction Master Receive mode Idle SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 202: Master Transmit With Repeated Start After Master Receive
Master Transmit mode Idle 7.2.6.2 I2C Slave Command Sequences Figure 7-13 presents the command sequence available for the I2C slave. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 203: Slave Command Sequence
0x0000.0007 (STOP, START, RUN). 9. Wait until the transmission completes by polling the BUSBSY bit of the I2CMCS register until the bit SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 204: Register Map
10. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged. Register Map Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 205: I2C Registers
I2C FIFO Status Section 7.3.1.25 FC0h I2CPP I2C Peripheral Properties Section 7.3.1.26 FC4h I2CPC I2C Peripheral Configuration Section 7.3.1.27 SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 206: I2Cmsa Register
1h = Receive The R/S bit specifies if the next master operation is a Receive (High) or Transmit (Low). Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 207: I2Cmcs Register
0h (R) = The I2C controller is not idle. 1h (W) = The bus transaction is a quick command. 1h (R) = The I2C controller is idle. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 208 1h (W) = The master is able to transmit or receive data. Note that this bit cannot be set in Burst mode. 1h (R) = The controller is busy. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 209: I2Cmdr Register
Table 7-6. I2CMDR Register Field Descriptions Field Type Reset Description 31-8 RESERVED DATA This byte contains the data transferred during a transaction. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 210: I2Cmtpr Register
SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the system clock period in ns. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 211: I2Cmimr Register
1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 212 1h = The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 213: I2Cmris Register
This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register. 0h = No interrupt 1h = The Arbitration Lost interrupt is pending. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 214 Value Description This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. 0h = No interrupt. 1h = A master interrupt is pending. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 215: I2Cmmis Register
This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Arbitration Lost interrupt was signaled and is pending. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 216 This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked clock timeout interrupt was signaled and is pending. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 217: I2Cmicr Register
Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS register and the STARTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 218 Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 219: I2Cmcr Register
1h = Master mode is enabled. RESERVED LPBK I2C Loopback 0h = Normal operation. 1h = The controller in a test mode loopback configuration. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 220: I2Cmclkocnt Register
This field contains the upper 8 bits of a 12-bit counter for the clock low timeout count. Note: The value of CNTL must be greater than 0x1. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 221: I2Cmbmon Register
1h = The I2CSDA signal is high. I2C SCL Status 0h = The I2CSCL signal is low. 1h = The I2CSCL signal is high. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 222: I2Cmblen Register
Transaction. If BURST is enabled this register must be set to a non-zero value otherwise an error will occur. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 223: I2Cmbcnt Register
Description 31-8 RESERVED CNTL I2C Master Burst Count This field contains the current count-down value of the BURST transaction. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 224: I2Csoar Register
Reset Description 31-7 RESERVED I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 225: I2Cscsr Register
1h (W) = Enables RX FIFO 1h (R) = The first byte following the slave s own address has been received. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 226 I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 227: I2Csdr Register
RESERVED DATA Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 228: I2Csimr Register
1h = The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CSRIS register is set. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 229 1h = Data interrupt sent to interrupt controller when DATARIS bit in the I2CSRIS register is set. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 230: I2Csris Register
This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register. 0h = No interrupt 1h = A transmit DMA complete interrupt is pending. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 231 This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. 0h = No interrupt. 1h = Slave Interrupt is pending. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 232: I2Csmis Register
0h = An interrupt has not occurred or is masked. 1h = An unmasked transmit DMA complete interrupt was signaled is pending. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 233 0h = An interrupt has not occurred or is masked. 1h = An unmasked slave data interrupt was signaled is pending. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 234: I2Csicr Register
Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 235 Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 236: I2Csoar2 Register
1h = Enables the use of the alternate address in the OAR2 field. OAR2 I2C Slave Own Address 2 This field specifies the alternate OAR2 address. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 237: I2Csackctl Register
0h = A response in not provided. 1h = An ACK or NACK is sent according to the value written to the ACKOVAL bit. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 238: I2Cfifodata Register
This field contains the current byte written to the TX FIFO. For back to back transmit operations, the application should not switch between writing to the I2CSDR register and the I2CFIFODATA. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 239: I2Cfifoctl Register
TX FIFO Flush Setting this bit will Flush the TX FIFO. This bit will self-clear when the flush has completed. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 240 5h = Trigger when TX FIFO 5 bytes 6h = Trigger when TX FIFO 6 bytes 7h = Trigger when TX FIFO 7 bytes Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 241: I2Cfifostatus Register
TXFE TX FIFO Empty 0h = The TX FIFO is not empty. 1h = The TX FIFO is empty. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 242: I2Cpp Register
31-1 RESERVED High-Speed Capable 0h = The interface is capable of Standard or Fast mode operation. 1h = Reserved. Inter-Integrated Circuit (I2C) Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 243: I2Cpc Register
0h = The interface is capable of Standard or Fast mode operation. 1h = Reserved. Must be set to 0 SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Circuit (I2C) Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 244: Spi (Serial Peripheral Interface)
Overview ..................Functional Description ................Initialization and Configuration .................. Access to Data Registers ..................Module Initialization ....................SPI Registers SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 245: Spi Block Diagram
PRCM module (refer to on clock-reset-power management). The subdivision of this clock is inside the SPI module. The CC3200 does not support waking up of the chip on SPI interface activity. This chapter focuses on the second SPI interface.
Page 246: Features
Each time a bit is transferred out from the master; one bit is transferred in from the slave. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 247: Spi Full Duplex Transmission (Example)
The baud rate of the SPI serial clock is programmable when SPI is a master. When SPI is operating as a slave, the serial clock SPICLK is an input from the external master. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 248: Phase And Polarity Combinations
SPI transfer for the SPI mode0 and SPI mode2, when SPI is master or slave, with the frequency of SPICLK equals the frequency of CLKSPIREF. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 249: Full Duplex Single Transfer Format With Pha = 0
SPI transfer for the SPI mode1 and SPI mode3, when SPI is master or slave, with the frequency of SPICLK equals the frequency of CLKSPIREF. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 250: Full Duplex Single Transfer Format With Pha = 1
MCSPI_XFERLEVEL[AEL]. The local host must perform the correct number of writes. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 251 When SPI is configured as a master device, the assertion of the SPIEN is optional, depending on the device connected to the controller. The following is a description of each configuration: SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 252: Contiguous Transfers With Spien Kept Active (2 Data Pins Interface Mode)
1 to 32768; in this case the duty cycle is always 50%. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 253: Clock Ratio Granularity
MCSPI_CHCONF[TRM] set to 0, and MCSPI_CHCONF[FFER] and MCSPI_CHCONF[FFEW] asserted. Then system can access a 32-byte depth FIFO per direction. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 254: Transmit/Receive Mode With No Fifo Used
Functional Description www.ti.com Figure 8-6. Transmit/Receive Mode With no FIFO Used Figure 8-7. Transmit/Receive Mode With Only Receive FIFO Enabled SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 255: Transmit/Receive Mode With Only Transmit Fifo Used
MCSPI_CHCONF[WL]. When DMA is used, the request is de-asserted after the first receive register read. No new request is asserted until it has performed the correct number of read accesses. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 256: Buffer Almost Full Level (Afl)
AEL and AFL levels, and the WCNT bit field to define the number of SPI word to be transferred using the FIFO before enabling the channel. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 257: 3-Pin Mode System Overview
In 3-pin mode, not all options related to chip select management are used: • MCSPI_CHxCONF[EPOL] • MCSPI_CHxCONF[TCS0] • MCSPI_CHxCONF[FORCE] The chip select pin SPIEN is forced to 0 in this mode. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 258: Slave Mode
(not updated with new data), and when an external master device starts a data transfer with SPI (transmit and receive). SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 259 In this last case, the definition of the AEL and AFL levels is based on 64 bytes, and is the responsibility of the local host. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 260: Interrupts
DMA request is asserted if the user has not performed the correct number of read accesses, as defined by SPI_XFERLEVEL[AFL]. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 261: Reset
Write new data into TX FIFO to transmit over the interface: SPIDataPut(GSPI_BASE,<UserData>); e. Read received data from the RX FIFO: SPIDataGet(GSPI_BASE,&<ulDummy>) f. Disable chip select: SPICSDisable(GSPI_BASE) SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 262: Slave Mode Operation With Interrupt
This section describes the supported data accesses (read or write) to and from the data receiver registers SPI_RX and data transmitter registers SPI_TX. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 263: Flow Chart - Module Initialization
Master normal, master turbo, slave • Transmit – receive • Write and read requests: interrupts, DMA • SPIEN lines assertion/deassertion: automatic, manual SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 264: Flow Chart - Common Transfer Sequence
In these sequences, some soft variables are used: • write_count = 0 • read_count. = 0 • channel_enable = FALSE • last_transfer = FALSE SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 265: Flow Chart - Transmit And Receive (Master And Slave)
For each flow, the host process contains the main process and the interrupt routine. This routine is called on the IRQ signals, or by an internal call if the module is used in polling mode. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 266 If they are not submultiples of N, the last request sizes are: • last_write_request_size ( < write_request_size ) • last_read_request_size. ( < read_request_size) SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 267: Flow Chart - Fifo Mode Common Sequence (Master)
These variables are initialized before starting the channel. 8.5.3.2 Transmit Receive with Word Count Flow of a transfer in transmit – receive mode, with word count. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 268: Flow Chart - Fifo Mode Transmit And Receive With Word Count (Master)
Figure 8-17. Flow Chart - FIFO Mode Transmit and Receive with Word Count (Master) 8.5.3.3 Transmit Receive without Word Count Flow of a transfer in transmit – receive mode, without word count. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 269: Flow Chart - Fifo Mode Transmit And Receive Without Word Count (Master)
SPI. All register offset addresses not listed in Table 8- should be considered as reserved locations, and the register contents should not be modified. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 270: Spi Register Description
Transfer Levels Register Section 8.6.1.11 8.6.1 SPI Register Description The remainder of this section lists and describes the SPI registers. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 271: Spi_Sysconfig Register
0h (R) = Reset done, no pending action 1h (W) = Initiate software reset 1h (R) = Reset (software or other) ongoing SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 272: Spi_Sysstatus Register
31-1 RESERVED RESETDONE Internal Reset Monitoring 0h (R) = Internal module reset is on-going 1h (R) = Reset completed SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 273: Spi_Irqstatus Register
0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 274 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 275: Spi_Irqenable Register
1h = Interrupt enabled TX_EMPTY_ENABLE Transmitter register empty or almost empty interrupt enable. 0h = Interrupt disabled 1h = Interrupt enabled SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 276: Spi_Modulctrl Register
Channel enable (master mode only) 1h = Channel will be used in master mode. This bit must be set in Force SPIEN mode. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 277: Spi_Chconf Register
0h = The buffer is not used to transmit data. 1h = The buffer is used to transmit data. 26-21 RESERVED SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 278 0h = SPIEN is held high during the active state. 1h = SPIEN is held low during the active state. SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 279 0h = Data are latched on odd numbered edges of SPICLK. 1h = Data are latched on even numbered edges of SPICLK. SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 280: Spi_Chstat Register
1h (R) = Register is empty Channel receiver register status 0h (R) = Register is empty 1h (R) = Register is full SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 281: Spi_Chctrl Register
FFh = Clock ratio is CLKD + 1 + 4080 RESERVED Channel enable 0h = Channel is not active 1h = Channel is active SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 282: Spi_Tx Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 8-15. SPI_TX Register Field Descriptions Field Type Reset Description 31-0 TDATA Channel data to transmit SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 283: Spi_Rx Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 8-16. SPI_RX Register Field Descriptions Field Type Reset Description 31-0 RDATA Channel received data SWRU367D – June 2014 – Revised May 2018 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 284: Spi_Xferlevel Register
SPI_XFERLEVEL[AEL] must be set with n-1. 0h = One byte 1h = 2 bytes Fh = 16 bytes SPI (Serial Peripheral Interface) SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 285: General-Purpose Timers
SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers ........................... Topic Page ......................Overview ....................Block Diagram ..................Functional Description ................Initialization and Configuration ....................TIMER Registers SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 286: Gptm Module Block Diagram
Programmable timers can be used to count or time external events that drive the timer input pins. The CC3200 general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or 32-bit GPTM block provides two 16-bit timers/counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer.
Page 287: Functional Description
Counters Timer A and Timer B are initialized to all 1s, along with their corresponding registers: ■ Load registers: • GPTM Timer A Interval Load (GPTMTAILR) register SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 288: Timer Modes
ISR entry by examining the snapshot values and the current value of the free-running timer. Snapshot mode is not available when the timer is configured in one-shot mode. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 289: Bit Timer With Prescaler Configurations
Based on this criteria, the maximum input frequency for edge detection is 1/4 of the frequency. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 290: Counter Values When The Timer Is Enabled In Input Edge-Count Mode
The last two edges are not counted, because the timer automatically clears the TnEN bit after the current count matches the value in the GPTMTnMATCHR register. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 291: Input Edge-Count Mode Example, Counting Down
GPTMTnV register holds the free-running timer value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 292: 16-Bit Input Edge-Time Mode Example
Table 9-7. Counter Values When the Timer is Enabled in PWM Mode Register Count Down Mode Count Up Mode GPTMTnR GPTMTnILR Not available GPTMTnV GPTMTnILR Not available General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 293: 16-Bit Pwm Mode Example
50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnILR=0xC350, and the match value is GPTMTnMATCHR=0x411A. Figure 9-4. 16-Bit PWM Mode Example SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 294: Dma Operation
The GPTM is configured for one-shot and periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making any General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 295: Input Edge-Count Mode
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3, and select a count direction by programming the TnCDIR bit. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 296: Pwm Mode
9. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 297: Timer Registers
Section 9.5.1.21 9.5.1 GPT Register Description This section lists and describes the GPT registers, in numerical order and by address offset. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 298: Www.ti.com
4h = For a 16/32-bit timer, this value selects the 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 5h - 7h = Reserved General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 299: Gptmtamr Register
CAEDMAEN bit in the GPTMDMAEV register, respectively. This bit is only valid in PWM mode. 0h = Capture event interrupt is disabled. 1h = Capture event interrupt is enabled. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 300 2:0 in the GPTMCFG register. 0h = Reserved 1h = One-shot timer mode 2h = Periodic timer mode 3h = Capture mode General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 301: Gptmtbmr Register
This bit is only valid in PWM mode. 0h = Capture event interrupt is disabled. 1h = Capture event is enabled. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 302 2:0 in the GPTMCFG register. 0h = Reserved 1h = One-shot timer mode 2h = Periodic timer mode 3h = Capture mode General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 303: Gptmctl Register
GPTM Timer A PWM Output Level. The TAPWML values are defined as follows: 0h = Output is unaffected. 1h = Output is inverted. RESERVED SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 304 0h = Timer A is disabled. 1h = Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 305: Gptmimr Register
GPTM Timer A DMA Done Interrupt Mask. The DMAAIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 306 GPTM Timer A Time-Out Interrupt Mask. The TATOIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 307: Gptmris Register
GPTM Timer A DMA Done Raw Interrupt Status 0h = The Timer A DMA transfer has not completed. 1h = The Timer A DMA transfer has completed. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 308 (0 or the value loaded into GPTMTAILR, depending on the count direction). General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 309: Gptmmis Register
0h = A Timer A mode match interrupt has not occurred or is masked. 1h = An unmasked Timer A mode match interrupt has occurred. RESERVED SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 310 0h = A Timer A time-out interrupt has not occurred or is masked. 1h = An unmasked Timer A time-out interrupt has occurred. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 311: Gptmicr Register
GPTM Timer A Capture Mode Match Interrupt Clear. Writing a 1 to this bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS bit in the GPTMMIS register. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 312 GPTM Timer A Time-Out Raw Interrupt. Writing a 1 to this bit clears the TATORIS bit in the GPTMRIS register and the TATOMIS bit in the GPTMMIS register. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 313: Gptmtailr Register
FFFFFFFFh GPTM Timer A Interval Load Register. Writing this field loads the counter for Timer A. A read returns the current value of GPTMTAILR. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 314: Gptmtbilr Register
Timer B. A read returns the current value of GPTMTBILR. When a 16/32-bit GPTM is in 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 315: Gptmtamatchr Register
Description 31-0 TAMR FFFFFFFFh GPTM Timer A Match Register. This value is compared to the GPTMTAR register to determine match events. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 316: Gptmtbmatchr Register
Description 31-0 TBMR FFFFh GPTM Timer B Match Register. This value is compared to the GPTMTBR register to determine match events. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 317: Gptmtapr Register
GPTM Timer A Prescale. The register loads this value on a write. A read returns the current value of the register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 318: Gptmtbpr Register
GPTM Timer B Prescale. The register loads this value on a write. A read returns the current value of this register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 319: Gptmtapmr Register
GPTMTAMATCHR to detect timer match events while using a prescaler. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler match value. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 320: Gptmtbpmr Register
RESERVED TBPSMR GPTM TimerB Prescale Match. This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 321: Gptmtar Register
In the input edge- time mode, this register contains the time at which the last edge event took place. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 322: Gptmtbr Register
In the input edge- time mode, this register contains the time at which the last edge event took place. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 323: Gptmtav Register
Note: In 16-bit mode, only the lower 16-bits of the GPTMTAV register can be written with a new value. Writes to the prescaler bits have no effect. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 324: Gptmtbv Register
In 16-bit mode, only the lower 16-bits of the GPTMTBV register can be written with a new value. Writes to the prescaler bits have no effect. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 325: Gptmdmaev Register
0h = Timer A RTC match DMA trigger is disabled. 1h = Timer A RTC match DMA trigger is enabled. SWRU367D – June 2014 – Revised May 2018 General-Purpose Timers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 326 Timer A dma_req signal is sent to the DMA on a time-out event. 0h = Timer A time-out DMA trigger is disabled. 1h = Timer A time-out DMA trigger is enabled. General-Purpose Timers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 327: Watchdog Timer
Topic Page ......................10.1 Overview ..................10.2 Functional Description ....................10.3 Register Map ............10.4 MCU Watch Dog Controller Usage Caveats SWRU367D – June 2014 – Revised May 2018 Watchdog Timer Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 328: Wdt Module Block Diagram
10.1 Overview The watchdog timer in CC3200 generates a regular interrupt or a reset when a time-out value is reached. The watchdog timer regains control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way.
Page 329: Functional Description
The watchdog timer is disabled by default out of reset. To achieve maximum watchdog protection of the device, the watchdog timer can be enabled at the start of the reset vector. NOTE: In the CC3200 R1 device, TI recommends that the application software, when rebooting after a WDT reset, requests the PRCM for hibernation (see Section 15.4.10) for 10 ms, and...
Page 330: Register Description
WDTLOCK 0x0000.0000 Watchdog Lock 10.3.1 Register Description This section lists and describes the WDT registers, in numerical order by address offset. Watchdog Timer SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 331: Watchdog Registers
Section 10.3.1.1.4 WDTRIS Watchdog Raw Interrupt Status Section 10.3.1.1.5 418h WDTTEST Watchdog Test Section 10.3.1.1.6 C00h WDTLOCK Watchdog Lock Section 10.3.1.1.7 SWRU367D – June 2014 – Revised May 2018 Watchdog Timer Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 332: Wdtload Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 10-3. WDTLOAD Register Field Descriptions Field Type Reset Description 31-0 WDTLOAD FFFFFFFFh Watchdog Load Value Watchdog Timer SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 333: Wdtvalue Register
Table 10-4. WDTVALUE Register Field Descriptions Field Type Reset Description 31-0 WDTVALUE FFFFFFFFh Watchdog Value Current value of the 32-bit down counter. SWRU367D – June 2014 – Revised May 2018 Watchdog Timer Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 334: Wdtctl Register
1h = Interrupt event enabled. Once enabled, all writes are ignored. Setting this bit enables the Watchdog Timer. Watchdog Timer SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 335: Wdticr Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 10-6. WDTICR Register Field Descriptions Field Type Reset Description 31-0 WDTINTCLR Watchdog Interrupt Clear SWRU367D – June 2014 – Revised May 2018 Watchdog Timer Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 336: Wdtris Register
WDTRIS Watchdog Raw Interrupt Status 0h = The watchdog has not timed out. 1h = A watchdog time-out event has occurred. Watchdog Timer SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 337: Wdttest Register
1h = If the microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. RESERVED SWRU367D – June 2014 – Revised May 2018 Watchdog Timer Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 338: Wdtlock Register
Resolution: The MCU application must detect a recovery from the WDOG trigger and force the device into complete hibernation with a wake-up associated with an internal RTC timer. This ensures a complete system cleanup. Watchdog Timer SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 339: Watchdog Flow Chart
10.4.2 System WatchDog Recovery Sequence The following sequence should be integrated in the user application for a reliable recovery from the WDOG trigger: SWRU367D – June 2014 – Revised May 2018 Watchdog Timer Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 340: System Watchdog Recovery Sequence
MCU Watch Dog Controller Usage Caveats www.ti.com Figure 10-10. System WatchDog Recovery Sequence Watchdog Timer SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 341: Sd Host Controller Interface
Initialization and Configuration Using Peripheral APIs .................. 11.5 Performance and Testing ..................11.6 Peripheral Library APIs ..................11.7 Register Description SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 342: 11.1 Overview
11.1 Overview The Secure Digital Host (SD Host) controller on the CC3200 provides an interface between a local host (LH) such as a microprocessor controller (MCU) and an SD memory card, and handles SD transactions with minimal LH intervention.
Page 343: Sdhost Controller Interface Block Diagram
This section discusses the host initialization and configuration example, followed by showing how the peripheral APs can implement the standard SD card detection and initialization sequence. SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 344: Basic Initialization And Configuration
!ulStatus ); // Check error status if(ulStatus &SDHOST_INT_ERRI) // Reset the command line SDHostCmdReset(SDHOST_BASE); return 1; else return 0; SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 345: Card Detection And Initialization
// Wait for card to become ready. // Send ACMD41 SendCmd(CMD_APP_CMD,0); ulRet = SendCmd(CMD_SD_SEND_OP_COND,0x40E00000); // Response contains 32-bit OCR register SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 346 == 0) ulRet = SendCmd(CMD_ALL_SEND_CID,0); if( ulRet == 0) SendCmd(CMD_SEND_REL_ADDR,0); SDHostRespGet(SDHOST_BASE,ulResp); Fill in the RCA CardAttrib->ulRCA = (ulResp[0] >> 16); SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 347: Block Read
SendCmd(CMD_READ_SINGLE_BLK, ulBlockNo) == 0 ) // Read out the data. while(ulSize--) MAP_SDHostDataRead(SDHOST_BASE,((unsigned long *)pBuffer); pBuffer+=4; else // Retutn error return 1; SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 348: 11.5 Performance And Testing
// Return error return 0; 11.5 Performance and Testing The APIs discussed above were tested with following cards types: SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 349: 11.6 Peripheral Library Apis
10485760 389741 2.97 11.6 Peripheral Library APIs This section lists the APIs, hosted in the CC3200 SDK (peripheral library) necessary for I2S configuration. void SDHostInit(unsigned long ulBase) • Description: This function configures the SD host module, enabling internal sub-modules. •...
Page 350 – SDHOST_INT_DEB: Data End Bit error – SDHOST_INT_CERR: Cart Status Error interrupt – SDHOST_INT_BADA: Bad Data error interrupt – SDHOST_INT_DMARD: Read DMA done interrupt SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 351 – ulSDHostClk – The rate of clock supplied to SD host module – ulCardClk – Required SD interface clock • Return: None SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 352 • Parameters: – ulBase – Base address of the SD host module SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 353: 11.7 Register Description
Register Description www.ti.com – pulData – Pointer to data word to be transferred • Return: None 11.7 Register Description SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 354: Sd-Host Registers
MMCHS_STAT Interrupt Status Section 11.7.1.14 234h MMCHS_IE Interrupt SD Enable Section 11.7.1.15 238h MMCHS_ISE Interrupt Signal Enable Section 11.7.1.16 SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 355: Mmchs_Csre Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 11-5. MMCHS_CSRE Register Field Descriptions Field Type Reset Description 31-0 CSRE Card status response error SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 356: Mmchs_Con Register
'command completion signal disable' token (such as mmci_cmd line held to 0 during 47 cycles followed by a 1). SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 357 0h = The host does not send an initialization sequence. 1h = The host sends an initialization sequence. RESERVED SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 358: Mmchs_Blk Register
1FFh = 511 bytes block length 200h = 512 bytes block length 3FFh = 1023 bytes block length 400h = 1024 bytes block length SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 359: Mmchs_Arg Register
Reset Description 31-0 Command argument bits [31:0] For CMD52, ARG must be programmed with IO_RW_DIRECT[39:8]. Refer to SDIO specification. SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 360: Mmchs_Cmd Register
Resume command 0h = Command with no data transfer 1h = Command with data transfer SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 361 This bit is used to enable DMA mode for host data access. 0h = DMA mode disable 1h = DMA mode enable SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 362: Mmchs_Rsp10 Register
Response [39:24] R2: Command Response [31:16] 15-0 RSP0 R1/R1b (normal response) /R3/R4/R5/R5b/R6 : Command Response [23:8] R2: Command Response [15:0] SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 363: Mmchs_Rsp32 Register
Table 11-11. MMCHS_RSP32 Register Field Descriptions Field Type Reset Description 31-16 RSP3 R2: Command Response [63:48] 15-0 RSP2 R2: Command Response [47:32] SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 364: Mmchs_Rsp54 Register
Table 11-12. MMCHS_RSP54 Register Field Descriptions Field Type Reset Description 31-16 RSP5 R2: Command Response [95:80] 15-0 RSP4 R2: Command Response [79:64] SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 365: Mmchs_Rsp76 Register
R1b (Auto CMD12 response): Command Response [39:24] R2: Command Response [127:112] 15-0 RSP6 R1b (Auto CMD12 response): Command Response [23:8] R2: Command Response [111:96] SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 366: Mmchs_Data Register
1 (MMCi.MMCHS_PSTATE[10] BWE bit), otherwise a bad access (MMCi.MMCHS_STAT[29] BADA bit) is signaled and the data is not written. SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 367: Mmchs_Pstate Register
0h = No valid data on the mmci_dat lines 1h = Read data transfer ongoing SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 368 0h = Issuing of command using mmci_cmd line is allowed 1h = Issuing of command using mmci_cmd line is not allowed SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 369: Mmchs_Hctl Register
7h = 3.3 V (typical) MMCHS2: This field must be set to 0x5 MMCHS3: This field must be set to 0x5 RESERVED SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 370: Mmchs_Sysctl Register
0h = Reset completed 1h = Software reset for all the designs 23-20 RESERVED SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 371 1h = The internal clock oscillates and can be automatically gated when MMCi.MMCHS_SYSCONFIG[0] AUTOIDLE bit is set to 1 (default value). SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 372: Mmchs_Stat Register
Write 0h = Status bit unchanged Read 1h = Card error Write 1h = Status is cleared 27-23 RESERVED SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 373 Read 0h = No error Write 0h = Status bit unchanged Read 1h = Time-out Write 1h = Status is cleared SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 374 Read 0h = No transfer complete Write 0h = Status bit unchanged Read 1h = Data transfer complete Write 1h = Status is cleared SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 375 Read 0h = No command complete Write 0h = Status bit unchanged Read 1h = Command complete Write 1h = Status is cleared SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 376: Mmchs_Ie Register
1h = The data time-out detection is enabled. RESERVED CEB_ENABLE Command end bit error interrupt enable 0h = Masked 1h = Enabled SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 377 Transfer completed interrupt enable 0h = Masked 1h = Enabled CC_ENABLE Command completed interrupt enable 0h = Masked 1h = Enabled SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 378: Mmchs_Ise Register
1h = Enabled RESERVED CEB_SIGEN Command end bit error signal status enable 0h = Masked 1h = Enabled RESERVED SD Host Controller Interface SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 379 Transfer completed signal status enable 0h = Masked 1h = Enabled CC_SIGEN Command completed signal status enable 0h = Masked 1h = Enabled SWRU367D – June 2014 – Revised May 2018 SD Host Controller Interface Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 380: Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port
..................12.2 Functional Description ..................12.3 Programming Model ............12.4 Peripheral Library APIs for I2S Configuration Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 381: Overview
12.1 Overview The CC3200 hosts a multi-channel audio serial port (MCASP). In this version of the device, only the Inter- Integrated Sound (I2S) bit stream format is supported. Given the nature of integration of this peripheral on the CC3200 platform, developers should use peripheral library APIs to control and operate the I2S block.
Page 382: Functional Description
MHz clock to the I2S module. The minimum frequency obtained by configuring this divider is (240000 KHz/1023.99) = 234.377 KHz. Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 383: I2S Data Port Interface
I2S_RX_DMA_PORT 0x4401E280 12.3.3 Initialization and Configuration I2S on the CC3200 acts as master providing frame sync and bit clock to slave and can operate in two modes: transmit-only mode and synchronous transmit – receive mode. In transmit-only mode, the device is only configured to transmit data. In synchronous transmit – receive mode, the device is configured to transmit and receive in a synchronous manner.
Page 384 // Check if there was a receive interrupt; if so read the data from the rx buffer and acknowledge // the interrupt if(ulStatus &I2S_STS_RDATA) I2SDataGetNonBlocking( I2S_BASE, I2S_DATA_LINE_1, &ulDummy); I2SIntClear(I2S_BASE,I2S_STS_RDATA); Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 385: Peripheral Library Apis For I2S Configuration
Peripheral Library APIs for I2S Configuration www.ti.com 12.4 Peripheral Library APIs for I2S Configuration This section describes the APIs hosted in the CC3200 SDK (Peripheral Library) necessary for I2S configuration. 12.4.1 Basic APIs for Enabling and Configuring the Interface void I2SDisable (unsigned long ulBase) Disables transmit and/or receive.
Page 386 The following parameters select the slot size: -I2S_SLOT_SIZE_24 -I2S_SLOT_SIZE_16 The following parameters select the data read/write port: -I2S_PORT_DMA -I2S_PORT_CPU Returns: Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 387 Peripheral Library APIs for I2S Configuration www.ti.com None. Reference: #define I2S_SLOT_SIZE_24 0x00B200B4 #define I2S_SLOT_SIZE_16 0x00700074 #define I2S_PORT_CPU 0x00000008 #define I2S_PORT_DMA 0x00000000 SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 388: Apis For Data Access If Dma Is Not Used
12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData) Waits to send data over the specified data line. Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 389 –1 is returned, and the application must retry the function later. Returns: Returns 0 on success, -1 otherwise. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 390: Apis For Setting Up, Handling Interrupts, Or Getting Status From I2S Peripheral
The ulIntFlags parameter has the same definition as the ulIntFlags parameter to I2SIntEnable(). Returns: None. Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 391 Table 12-1 lists the values that can be passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags parameter. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 392: Ulintflags Parameter
Rx buffer and ready to be serviced by the CPU or DMA. When RDATA is set, it always causes a DMA event. Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 393 XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. I2S_STS_RDMA 0x40000000 SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 394: Apis To Control Fifo Structures Associated With I2S Peripheral
12.4.4.4 void I2STxFIFODisable (unsigned long ulBase) Disables transmit FIFO. Parameters: ulBase — is the base address of the I2S module. Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 395 This function gets the number of 32-bit words currently in the transmit FIFO. Returns: Returns transmit FIFO status. SWRU367D – June 2014 – Revised May 2018 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 396: Analog-To-Digital Converter [Adc]
ADC Register Mapping ................... 13.4 ADC_MODULE Registers ................13.5 Initialization and Configuration ............13.6 Peripheral Library APIs for ADC Operation Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 397: Overview
13.1 Overview The CC3200 provides a general purpose, multi-channel Analog-to-Digital Converter (ADC). Each of the ADC channels supports 12-bit conversion resolution with sampling periodicity of 16 uS (62.5 Ksps/channel). Each channel has an associated FIFO and DMA. For detailed electrical characteristics of the ADC, refer to the CC3200 data sheet (SWAS032).
Page 398: Adc Register Mapping
The remaining channels (odd) are used for monitoring various internal levels by the SimpleLink subsystem in CC3200 SoC. Register bits and functions related to these internal channels are marked as reserved in the register description. These bits must not be modified by application code to ensure proper functioning of the system.
Page 399: Adc_Module Registers
13.4.1 ADC Register Description The remainder of this section lists and describes the ADC registers, in numerical order by address offset. SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 400: Adc_Ctrl Register
R-0h R/W-0h Table 13-3. ADC_CTRL Register Field Descriptions Field Type Reset Description 31-1 RESERVED ADC_EN_APPS ADC enable for application processor Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 401: Adc_Ch0_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 402: Adc_Ch2_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 403: Adc_Ch4_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 404: Adc_Ch6_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 405: Adc_Ch0_Irq_Status Register
Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 406: Adc_Ch2_Irq_Status Register
Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 407: Adc_Ch4_Irq_Status Register
Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 408: Adc_Ch6_Irq_Status Register
Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 409: Adc_Dma_Mode_En Register
Bit 7: Reserved for internal channel. 0h = Only the interrupt mode is enabled. 1h = Respective ADC channel is enabled for DMA. SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 410: Adc_Timer_Configuration Register
1h = Timer is enabled TIMERRESET 1h = Reset timer 23-0 TIMERCOUNT 111111h Timer count configuration. 17-bit counter is supported. Other MSBs are redundant. Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 411: Adc_Timer_Current_Count Register
TIMERCURRENTCOUNT R-0h R-0h Table 13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions Field Type Reset Description 31-17 RESERVED 16-0 TIMERCURRENTCOUNT Timer count configuration SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 412: Channel0Fifodata Register
[1:0] : Reserved [13:2] : ADC sample Bits [30:14]: Timestamp per ADC sample [31] : Reserved Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 413: Channel2Fifodata Register
[1:0] : Reserved [13:2] : ADC sample Bits [30:14]: Timestamp per ADC sample [31] : Reserved SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 414: Channel4Fifodata Register
[1:0] : Reserved [13:2] : ADC sample Bits [30:14]: Timestamp per ADC sample [31] : Reserved Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 415: Channel6Fifodata Register
[1:0] : Reserved [13:2] : ADC sample Bits [30:14]: Timestamp per ADC sample [31] : Reserved SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 416: Adc_Ch0_Fifo_Lvl Register
This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4. Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 417: Adc_Ch2_Fifo_Lvl Register
This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4. SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 418: Adc_Ch4_Fifo_Lvl Register
This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4. Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 419: Adc_Ch6_Fifo_Lvl Register
This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4. SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 420: Initialization And Configuration
4. Enable the ADC module ADCEnable(ADC_BASE) 5. Read out the ADC samples using following code if( ADCFIFOLvlGet(ADC_BASE, ADC_CH_1) ) ulSample = ADCFIFORead(ADC_BASE, ADC_CH_1) Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 421: Peripheral Library Apis For Adc Operation
13.6 Peripheral Library APIs for ADC Operation 13.6.1 Overview Four out of the eight channels of the ADC in the CC3200 are used internally for the SimpleLink subsystem (NWP and Wi-Fi). TI encourages applications to access the four external ADC channels through the peripheral library APIs.
Page 422: Apis For Data Transfer [Direct Access To Fifo And Dma Setup]
Gets the current FIFO level for a specified ADC channel. Parameters: ulBase Base address of the ADC ulChannel One of the valid ADC channels Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 423 None. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel) Disables the ADC DMA operation for a specified channel. Parameters: SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 424: Apis For Interrupt Usage
Base address of the ADC ulChannel One of the valid ADC channels ulIntFlags The bit mask of the interrupt sources to be enabled Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 425 Returns: • None 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel) Gets the current channel interrupt status. Parameters: SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 426: Apis For Setting Up Adc Timer For Time Stamping The Samples
• None 13.6.6.2 void ADCTimerDisable (unsigned long ulBase) Disables the ADC internal timer. Parameters: ulBase Base address of the ADC Analog-to-Digital Converter [ADC] SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 427 This function gets the current value of the 17-bit ADC internal timer. Returns: • Returns the current value of the ADC internal timer. SWRU367D – June 2014 – Revised May 2018 Analog-to-Digital Converter [ADC] Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 428: Parallel Camera Interface Module
..................14.4 Programming Model ..................... 14.5 Interrupt Handling ............ 14.6 Camera Interface Module Functional Registers .................... 14.7 Developer’s Guide Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 429: Overview
14.1 Overview The CC3200 camera core module can interface an external image sensor. It supports an 8-bit parallel image sensor interface (Non-BT) interface with vertical and horizontal synchronization signals. BT mode is not supported. The recommended maximum pixel clock is 1 MHz. The module stores the image data in a FIFO and can generate DMA requests.
Page 430: Functional Description
1 to ensure a clean acquisition of the frame. Data is accepted as long as CAM_P_HS and CAM_P_VS are both active (when CC_CTRL.NOBT_SYNCHRO is cleared 0): Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 431: Different Scenarios Of Cam_P_Hs And Cam_P_Vs
The camera core module supports decimation from the image sensor where CAM_P_HS toggles between pixels. Figure 14-5. CAM_P_HS Toggles Between Pixels in Decimation Figure 14-6. Parallel Camera I/F State Machine SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 432: Fifo Buffer
2. Reset the FIFOs and DMA control – The internal state machines of the FIFO and the DMA control Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 433: Clock Generation
CPU of the data transfers. The module can generate a DMA request when the FIFO reaches the threshold programmed into CC_CTRL_DMA.FIFO_THRESHOLD. SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 434: Programming Model
4. Enable the picture acquisition using the CC_CTRL. TI recommends setting CC_FRAME_TRIG and NOBT_SYNCHRO to 1 when CC_EN is set to 1, to start the acquisition. If software only acquires one Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 435: Disable The Picture Acquisition
4. Set the CC_CTRL.CC_EN bit to 1, to re-enable the data flow from the image sensor. If an underflow occurs, the entire data flow path must be reset to restart cleanly. SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 436: Camera Interface Module Functional Registers
The remainder of this section lists and describes the camera interface module functional registers, in numerical order by address offset. Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 437: Cc_Sysconfig Register
0h = OCP clock is free-running 1h = Automatic OCP clock gating strategy is applied, based on the OCP interface activity SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 438: Cc_Sysstatus Register
Reset Description 31-1 RESERVED ResetDone Internal Reset Monitoring 0h = Internal module reset is ongoing. 1h = Reset completed Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 439: Cc_Irqstatus Register
0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 440 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 441: Cc_Irqenable Register
False Synchronization Code Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs RESERVED SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 442 FIFO_UF_IRQ_EN FIFO Underflow Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 443: Cc_Ctrl Register
By writing 0 to this field, the module is disabled at the end of the frame if CC_FRAME_TRIG = 1, and is disabled immediately if CC_FRAME_TRIG = 0. 15-14 RESERVED SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 444 011h = Reserved 100h = Parallel BT 8-bit 101h = Parallel BT 10-bit 110h = Reserved 111h = FIFO test mode. Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 445: Cc_Ctrl_Dma Register
0000000h = Threshold set to 1 0000001h = Threshold set to 2 1111111h = Threshold set to 128 SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 446: Cc_Ctrl_Xclk Register
00001h = CAM_XCLK Stable high level from 2 to 30 = CAM_XCLK = CAM_MCLK / XCLK DIV 11111h = Bypass - CAM_XCLK = CAM_MCLK Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 447: Peripheral Library Apis
31-0 FIFO_DATA Reads/writes the 32-bit word from/into the FIFO. 14.6.2 Peripheral Library APIs This section lists the software APIs hosted in the CC3200 SDK (peripheral library) for configuring and using the camera interface module. void CameraReset(unsigned long ulBase) • Description: This function resets the camera core.
Page 448 CameraIntUnregister(unsigned long ulBase) • Description: This function unregisters and disables the global camera interrupt from the interrupt controller. • Parameters: Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 449 Description: This function stops the image capture over the camera interface. The capture is stopped either immediately or at the end of the current frame, based on the bImmediate parameter. • Parameters: SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 450: Developer's Guide
7. For handling the image data that is not a multiple of a FIFO threshold, the frame-end interrupt must be registered using the peripheral API CameraIntEnable. This generates an interrupt at the end of every frame: Parallel Camera Interface Module SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 451 (void *)<data_buffer>, UDMA_DST_INC_32); else(<check condition for odd iterations>) DMASetupTransfer(UDMA_CH22_CAMERA|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, <total_dma_elements>, UDMA_SIZE_32, UDMA_ARB_8, (void *)CAM_BUFFER_ADDR, UDMA_SRC_INC_32, (void *)<data_buffer>, UDMA_DST_INC_32); SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 452: Using Peripheral Driver Apis For Communicating With Image Sensors
Most image sensors provide a two-wire serial interface for external MCUs to control them. This section shows how to use the CC3200 I2C interface to communicate with these image sensors. The CC3200 includes one I2C module operating with standard (100-Kbps) or fast (400-Kbps) transmission speeds.
Page 453 – bMasked is false if the raw interrupt status is requested, and true if the masked interrupt status is requested. SWRU367D – June 2014 – Revised May 2018 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 454: Power, Reset And Clock Management
Power Management Control Architecture ...................... 15.4 PRCM APIs ..................... 15.5 Peripheral Macros ................. 15.6 Power Management Framework ....................15.7 PRCM Registers Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 455: Trademarks
AMBA, CoreSight are trademarks of ARM Limited. 15.2 Overview The CC3200 SoC incorporates a highly optimized on-chip power management unit capable of operating directly from battery, without any external regulator. The on-chip PMU includes a set of high-efficiency, fast transient response DC-DC converters, LDOs, and reference voltage generators.
Page 456: Power Management Unit Supports Two Supply Configurations
Hibernate controller: Implements the lowest current sleep mode of the chip (hibernate mode), and consists of the following functions: – Chip wake-up controller – RTC counter and RTC-based wakeup Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 457: Supply Brownout And Blackout
– Not directly accessible from the application processor – PMU state transitions are initiated by control signals from the PRCM Refer to the CC3200 data sheet (SWAS032) for the chip wake-up sequence and timing parameters. 15.2.3 Supply Brownout and Blackout BROWNOUT is the state where the supply voltage falls below the chip brownout threshold.
Page 458 The system can subsequently be made to restart on a RTC timer, on a chip reset, or on plugging of new batteries. For CC3200 applications where battery life is critical, maximize the fraction of time spent in LPDS or hibernate modes compared to active and other sleep modes (SLEEP, DEEPSLEEP).
Page 459: Power Management Control Architecture
While this repeats in multiples of the beacon period (104 mS), the application processor may implement its own sleep strategy with a different periodicity. An advanced power management scheme has been implemented at the CC3200 chip level. This scheme handles the asynchronous sleep-wake requirements of multiple processors and Wi-Fi radio subsystems in a way that is transparent to the software, yet energy efficient.
Page 460 Table 15-1 shows the feasible combinations of power states between the application processor and the network (including WLAN) subsystems. Refer to the CC3200 data sheet (SWAS032) for details of current consumption for these combinations. Table 15-1. Possible PM State Combinations of Application Processor and Network Subsystem...
Page 461: Global Power-Reset-Clock Manager (Gprcm)
Power Management Control Architecture www.ti.com Figure 15-3 shows the high-level architecture of the CC3200 SoC-level power management. Figure 15-3. Power Management Control Architecture in CC3200 15.3.1 Global Power-Reset-Clock Manager (GPRCM) The global power-reset-clock manager module (GPRCM) receives the sleep requests from the subsystems and the wake events from associated sources.
Page 462: Application Reset-Clock Manager (Arcm)
Section 15.7. 15.4 PRCM APIs This section gives an overview of the PRCM APIs provided in the CC3200 Software Development Kit peripheral library. For more details, refer to the SDK documentation. 15.4.1 MCU Initialization Booting from power-off or exiting hibernate low power mode, the user application can configure the mandatory MCU parameters by calling void PRCMCC3200MCUInit() API.
Page 463: Clock Control
Return: None 15.4.6 Low Power Modes SRAM Retention – The CC3200 SRAM is organized in 4 × 64-KB columns. By default, all SRAM columns are configured to be retained across LPDS and deep sleep power modes. The application can enable or...
Page 464: Sleep (Sleep)
15.4.9 Low-Power Deep Sleep (LPDS) In this mode, the MCU core and its associated peripheral are reset with selective SRAM column retention. Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 465 Parameter: None Return: Returns the LPDS wake-up cause enumerated as one of the following: • PRCM_LPDS_HOST_IRQ: Interrupt from NWP SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 466: Hibernate (Hib)
PRCM_HIB_GPIO2: GPIO 2 • PRCM_HIB_GPIO4: GPIO 4 • PRCM_HIB_GPIO13: GPIO 13 • PRCM_HIB_GPIO17: GPIO 17 • PRCM_HIB_GPIO11: GPIO 11 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 467 Parameter: ullTicks: Wake-up interval in 32.768-KHz ticks SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 468: Slow Clock Counter
Return: Returns a 32-bit value read from a specified OCR register. 15.4.11 Slow Clock Counter The CC3200 has a 48-bit on-chip always-on slow counter running at 32.768 KHz, which can wake up the device from hibernate low-power mode, or generate an interrupt to the core on counting a particular match value.
Page 469: Power Management Framework
I2C interface 15.6 Power Management Framework The CC3200 SDK comes with a power management software framework. This framework provides simple services that can be invoked by the application, and callback functions that can be overridden by the application code. For details refer to the Power Management framework software documentation.
Page 470: Prcm Registers
Section 15.7.1.39 I2CLCKEN Section 15.7.1.40 I2CSWRST Section 15.7.1.41 LPDSREQ Section 15.7.1.42 TURBOREQ Section 15.7.1.43 108h DSLPWAKECFG Section 15.7.1.44 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 471: Prcm Register Description
15.7.1 PRCM Register Description The remainder of this section lists and describes the PRCM registers, in numerical order by address offset. SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 472: Camclkcfg Register
010h = 3 011h = 4 100h = 5 101h = 6 110h = 7 111h = 8 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 473: Camclken Register
RUNCLKEN CAMERA_RUN_CLK_ENABLE 0h = Disable camera clk during run mode 1h = Enable camera clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 474: Camswrst Register
1h = Camera clocks/resets are enabled SWRST CAMERA_SOFT_RESET 0h = De-assert reset for Camera-core 1h = Assert reset for Camera-core Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 475: Mcaspclken Register
RUNCLKEN MCASP_RUN_CLK_ENABLE 0h = Disable MCASP clk during run mode 1h = Enable MCASP clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 476: Mcaspswrst Register
1h = MCASP Clocks/resets are enabled SWRST MCASP_SOFT_RESET 0h = De-assert reset for MCASP-core 1h = Assert reset for MCASP-core Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 477: Sdiomclkcfg Register
010h = 3 011h = 4 100h = 5 101h = 6 110h = 7 111h = 8 SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 478: Sdiomclken Register
RUNCLKEN MMCHS_RUN_CLK_ENABLE 0h = Disable MMCHS clk during run mode 1h = Enable MMCHS clk during run mode Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 479: Sdiomswrst Register
1h = MMCHS Clocks and resets are enabled SWRST MMCHS_SOFT_RESET 0h = De-assert reset for MMCHS-core 1h = Assert reset for MMCHS-core SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 480: Apspiclkcfg Register
010h = 3 011h = 4 100h = 5 101h = 6 110h = 7 111h = 8 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 481: Apspiclken Register
RUNCLKEN MCSPI_A1_RUN_CLK_ENABLE 0h = Disable MCSPI_A1 clk during run mode 1h = Enable MCSPI_A1 clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 482: Apspiswrst Register
1h = MCSPI_A1 Clocks and resets are enabled SWRST MCSPI_A1_SOFT_RESET 0h = De-assert reset for MCSPI_A1-core 1h = Assert reset for MCSPI_A1-core Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 483: Dmaclken Register
RUNCLKEN UDMA_A_RUN_CLK_ENABLE 0h = Disable UDMA_A clk during run mode 1h = Enable UDMA_A clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 484: Dmaswrst Register
1h = UDMA_A Clocks and resets are enabled SWRST UDMA_A_SOFT_RESET 0h = De-assert reset for DMA_A 1h = Assert reset for DMA_A Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 485: Gpio0Clken Register
RUNCLKEN GPIO_A_RUN_CLK_ENABLE 0h = Disable GPIO_A clk during run mode 1h = Enable GPIO_A clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 486: Gpio0Swrst Register
1h = GPIO_A Clocks and resets are enabled SWRST GPIO_A_SOFT_RESET 0h = De-assert reset for GPIO_A 1h = Assert reset for GPIO_A Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 487: Gpio1Clken Register
RUNCLKEN GPIO_B_RUN_CLK_ENABLE 0h = Disable GPIO_B clk during run mode 1h = Enable GPIO_B clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 488: Gpio1Swrst Register
1h = GPIO_B Clocks and resets are enabled SWRST GPIO_B_SOFT_RESET 0h = De-assert reset for GPIO_B 1h = Assert reset for GPIO_B Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 489: Gpio2Clken Register
RUNCLKEN GPIO_C_RUN_CLK_ENABLE 0h = Disable GPIO_C clk during run mode 1h = Enable GPIO_C clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 490: Gpio2Swrst Register
1h = GPIO_C Clocks and resets are enabled SWRST GPIO_C_SOFT_RESET 0h = De-assert reset for GPIO_C 1h = Assert reset for GPIO_C Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 491: Gpio3Clken Register
RUNCLKEN GPIO_D_RUN_CLK_ENABLE 0h = Disable GPIO_D clk during run mode 1h = Enable GPIO_D clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 492: Gpio3Swrst Register
1h = GPIO_D Clocks and resets are enabled SWRST GPIO_D_SOFT_RESET 0h = De-assert reset for GPIO_D 1h = Assert reset for GPIO_D Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 493: Gpio4Clken Register
RUNCLKEN GPIO_E_RUN_CLK_ENABLE 0h = Disable GPIO_E clk during run mode 1h = Enable GPIO_E clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 494: Gpio4Swrst Register
1h = GPIO_E Clocks and resets are enabled SWRST GPIO_E_SOFT_RESET 0h = De-assert reset for GPIO_E 1h = Assert reset for GPIO_E Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 495: Wdtclken Register
RUNCLKEN WDOG_A_RUN_CLK_ENABLE 0h = Disable WDOG_A clk during run mode 1h = Enable WDOG_A clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 496: Wdtswrst Register
1h = WDOG_A Clocks and resets are enabled SWRST WDOG_A_SOFT_RESET 0h = De-assert reset for WDOG_A 1h = Assert reset for WDOG_A Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 497: Uart0Clken Register
UART0RCLKEN UART_A0_RUN_CLK_ENABLE 0h = Disable UART_A0 clk during run mode 1h = Enable UART_A0 clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 498: Uart0Swrst Register
1h = UART_A0 Clocks and resets are enabled SWRST UART_A0_SOFT_RESET 0h = De-assert reset for UART_A0 1h = Assert reset for UART_A0 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 499: Uart1Clken Register
RUNCLKEN UART_A1_RUN_CLK_ENABLE 0h = Disable UART_A1 clk during run mode 1h = Enable UART_A1 clk during run mode SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 500: Uart1Swrst Register
SWRST UART_A1_SOFT_RESET 0h = De-assert the soft reset for UART_A1 1h = Assert the soft reset for UART_A1 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 501: Gpt0Clkcfg Register
RUNCLKEN GPT_A0_RUN_CLK_ENABLE 0h = Disable the GPT_A0 clock during run 1h = Enable the GPT_A0 clock during run SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 502: Gpt0Swrst Register
SWRST GPT_A0_SOFT_RESET 0h = De-assert the soft reset for GPT_A0 1h = Assert the soft reset for GPT_A0 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 503: Gpt1Clken Register
RUNCLKEN GPT_A1_RUN_CLK_ENABLE 0h = Disable the GPT_A1 clock during run 1h = Enable the GPT_A1 clock during run SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 504: Gpt1Swrst Register
SWRST GPT_A1_SOFT_RESET 0h = De-assert the soft reset for GPT_A1 1h = Assert the soft reset for GPT_A1 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 505: Gpt2Clken Register
RUNCLKEN GPT_A2_RUN_CLK_ENABLE 0h = Disable the GPT_A2 clock during run 1h = Enable the GPT_A2 clock during run SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 506: Gpt2Swrst Register
SWRST GPT_A2_SOFT_RESET 0h = De-assert the soft reset for GPT_A2 1h = Assert the soft reset for GPT_A2 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 507: Gpt3Clken Register
RUNCLKEN GPT_A3_RUN_CLK_ENABLE 0h = Disable the GPT_A3 clock during run 1h = Enable the GPT_A3 clock during run SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 508: Gpt3Swrst Register
SWRST GPT_A3_SOFT_RESET 0h = De-assert the soft reset for GPT_A3 1h = Assert the soft reset for GPT_A3 Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 509: Mcaspclkcfg0 Register
(Fref/Freq) can be represented as = I.F where I is the integer part of the ratio and F is the fractional part of the ratio. SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 510: Mcaspclkcfg1 Register
RESERVED SPARE MCASP_FRAC_DIV_PERIOD. This bitfield is not used in HW. Can be used as a spare RW register. Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 511: I2Clcken Register
RUNCLKEN I2C_RUN_CLK_ENABLE 0h = Disable the I2C clock during run 1h = Enable the I2C clock during run SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 512: I2Cswrst Register
SWRST I2C_SOFT_RESET 0h = De-assert the soft reset for Shared-I2C 1h = Assert the soft reset for Shared-I2C Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 513: Lpdsreq Register
Table 15-45. LPDSREQ Register Field Descriptions Field Type Reset Description 31-1 RESERVED LPDSREQ APPS_LPDS_REQ 1h = Request for LPDS SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 514: Turboreq Register
Table 15-46. TURBOREQ Register Field Descriptions Field Type Reset Description 31-1 RESERVED TURBOREQ APPS_TURBO_REQ 1h = Request for TURBO Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 515: Dslpwakecfg Register
0h = Disable deep-sleep wake timer in APPS RCM 1h = Enable deep-sleep wake timer in APPS RCM for deep-sleep SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 516: Dslptimrcfg Register
OPP during deep-sleep exit. 15-0 TIMRCFG DSLP_WAKE_TIMER_WAKE_CFG Configuration (in slow_clks) which indicates when to request for WAKE during deep-sleep exit. Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 517: Slpwakeen Register
0h = Disable the sleep wakeup due to sleep-timer 1h = Enable the sleep wakeup due to sleep-timer SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 518: Slptmrcfg Register
Table 15-50. SLPTMRCFG Register Field Descriptions Field Type Reset Description 31-0 TMRCFG SLP_WAKE_TIMER_CFG Configuration (number of sysclks-80MHz) for the Sleep wake-up timer. Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 519: Wakenwp Register
NWP (When NWP is in any of its low- power modes : SLP/DSLP/LPDS) SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 520: Rcm_Is Register
1h = Indicates that NWP had caused the wakeup from deep-sleep. EXITSLPBYNWP apps_sleep_wake_from_nwp 1h = Indicates that NWP had caused the wakeup from Sleep Power, Reset and Clock Management SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 521: Rcm_Ien Register
RESERVED PLLLOCKIRQ 0h = Mask this interrupt 1h = Unmask Interrupt to Apps processor when PLL is locked. SWRU367D – June 2014 – Revised May 2018 Power, Reset and Clock Management Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 522: I/O Pads And Pin Multiplexing
Analog Mux Control Registers ................16.6 Pins Available for Applications ..............16.7 Functional Pin Mux Configurations ................. 16.8 Pin Mapping Recommendations I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 523: Overview
• Configurable pullup and pulldown (10-uA nominal) • Software configurable pad state retention during LPDS Each I/O pad cell in the CC3200 has the following ports: • PAD: I/O pad connected to package pin and external components • ODI: Level-shifted data from from PAD to core logic •...
Page 524: Gpio Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53
High-level source current, V = 2.4 2-mA Drive 4-mA Drive 6-mA Drive 8-mA Drive 10-mA Drive 12-mA Drive 14-mA Drive I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 525: Analog-Digital Pin Multiplexing
RF sensitivity and performance. The default drive-strength setting is 6 mA. 16.3 Analog-Digital Pin Multiplexing The CC3200 implements an advanced analog-digital pin multiplexing scheme to maximize the number of functional signals in a compact 64-pin QFN package. Pins are multiplexed with analog-test, RF-test, clock and power-management functionalities.
Page 526: Special Ana/Dig Pins
These modules use automatic configuration sensing. Thus, some board-level configuration is required to use pin 45 and pin 52 as digital pads. This is shown in Figure 16-2. I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 527: Board Configuration To Use Pins 45 And 52 As Digital Signals
TI recommends that pin 52 is used for output-only functionalities. Figure 16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 528: Pin 29 And 30
16.4.2 Pin 29 and 30 Pin 29 and pin 30 are reserved for WLAN antenna diversity. These pins control an external RF switch, which multiplexes the RF pin of the CC3200 between two antennas. These pins should not be used for other functions.
Page 529: Board Level Behavior
Digital I/O cell is directly connected but (1.8-V absolute max. 1.46-V full scale) like other digital I/Os. Hi-Z. SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 530: Pins Available For Applications
GPIO17 VDD_DIG1 VIN_IO1 FLASH_SP I_CLK FLASH_SP I_DOUT FLASH_SP I_DIN FLASH_SP I_CS GPIO22 GPIO28 SOP2 (TCXO_EN (TCXO_EN (TCXO_EN (TCXO_EN I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 531 DCDC_PA _SW_P DCDC_PA _SW_N DCDC_PA _OUT DCDC_DI G_SW VIN_DCDC _DIG DCDC_AN A2_SW_P DCDC_AN A2_SW_N VDD_ANA VDD_ANA VDD_RAM GPIO0 SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 532: Functional Pin Mux Configurations
GPIO9 (THERMAL PAD) Total available for application 16.7 Functional Pin Mux Configurations Pin mux configurations supported in the CC3200 are listed in Table 16-7. I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback...
Page 533: Pin Multiplexing
LPDS mode: The state of unused GPIOs in LPDS is input with 500-kΩ pulldown. For all used GPIOs , the user can enable internal pulls, which would hold them in a valid state. Hibernate mode: The CC3200 device leaves the digital pins in a Hi-Z state without any internal pulls when the device enters hibernate state. This can cause glitches on output lines, unless held at valid levels by external resistors.
Page 534 General SPI Hi-Z Hi-Z Hi-Z (0x4402 E0D8) Clock pDATA8 Parallel Camera (CAM_D4) Data Bit 4 GT_CCP05 Timer Capture Port I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 535 SD Card Command Line pDATA11 Parallel Camera (CAM_D7) Data Bit 7 Internal Digital VDD_DIG1 Int pwr VDD_DIG1 Core Voltage SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 536 GPIO23 GPIO_PAD_CONFIG_ with Hi-Z Hi-Z JTAG UART1_TX UART1 TX Data (0x4402 E0FC) I2C_SCL I2C Clock Hi-Z (Open Drain) I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 537 Modulated O/P JATG/SWD TMS MUXed Reset Default with GPIO_PAD_CONFIG_ Pinout JTAG/S Hi-Z Hi-Z Hi-Z (0x4402 E114) GPIO29 General-Purpose TMSC SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 538 (0x4402 E10C) For details on proper use, see the Drive Strength and Reset States for Analog-Digital Multiplexed Pins section of the CC3200 data sheet (SWAS032). This pin is one of three that must have a passive pullup or pulldown resistor on board to configure the chip hardware power-up mode. Because of this, if this pin is used for digital functions, it must be output only.
Page 539 DIG DC-DC Power switching node DIG DC-DC input VIN_DCDC_ Supply VIN_DCDC_DI (connected to Input chip input supply [VBAT]) SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 540 VDD_FLASH must be shorted to V supply For details on proper use, see the Drive Strength and Reset States for Analog-Digital Multiplexed Pins section of the CC3200 data sheet (SWAS032). I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright ©...
Page 541 I2S Audio Port Hi-Z Data 0 (RX/TX) Connect 32.768- kHz XTAL or RTC_XTAL_ RTC_XTAL_P Froce external Clock CMOS level clock SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 542 (11) To use the digital functions, RTC_XTAL_N must be pulled high to V using a 100-KΩ resistor supply I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 543 Requires user configuration to enable the ADC channel analog switch. (The switch is off by default.) The digital I/O is always connected, and must be made Hi-Z before enabling the ADC switch. (15) For details on proper use, see the Drive Strength and Reset States for Analog-Digital Multiplexed Pins section of the CC3200 data sheet (SWAS032). SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright ©...
Page 544 Requires user configuration to enable the ADC channel analog switch. (The switch is off by default.) The digital I/O is always connected, and must be made Hi-Z before enabling the ADC switch. (19) For details on proper use, see the Drive Strength and Reset States for Analog-Digital Multiplexed Pins section of the CC3200 data sheet (SWAS032). I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright ©...
Page 545 GPIO_PAD_CONFIG_ support) GPIO8 Hi-Z Hi-Z Hi-Z (0x4402 E0C0) McAFSX I2S Audio Port Frame Sync GT_CCP06 Timer Capture Port SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 546: Pin Mapping Recommendations
16.8 Pin Mapping Recommendations For certain high speed interfaces, TI recommends using the following pin groups. Recommended pin groups for I2S: I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 547: Pad Configuration Registers For Application Pins
Pins are referred either by number or by the GPIO mapped to that pin. Functionalities available on a pin are not limited to that name. Refer to the pin-mux table for all possible functional mapping. SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 548: Gpio_Pad_Config_0 To Gpio_Pad_Config_32 Register Description
16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions 16.8.1.1.1 GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Table 16-12. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description Field Type Reset Description 31-12 Reserved I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 549: Pad Behavior During Reset And Hibernate
PM functions. 16.8.3 Control Architecture The I/O pad data and control path architecture in the CC3200 is shown in Figure 16-3.
Page 550: Cc3200 Pin-Mux Examples
Pin Mapping Recommendations www.ti.com Figure 16-3. I/O Pad Data and Control Path Architecture in CC3200 16.8.4 CC3200 Pin-mux Examples Table 16-13 shows recommended pin-out for several application classes. I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright ©...
Page 551: Recommended Pin Multiplexing Configurations
Pin Mapping Recommendations www.ti.com Table 16-13. Recommended Pin Multiplexing Configurations CC3200 Recommended Pinout Grouping Use – Examples Home Wifi Audio ++ Sensor-Tag Home Wifi Audio ++ WiFi Remote Sensor Door- Industrial Industrial Industrial GPIOs Security High- Industrial Security Toys Industrial...
Page 552 Pin Mapping Recommendations www.ti.com Table 16-13. Recommended Pin Multiplexing Configurations (continued) CC3200 Recommended Pinout Grouping Use – Examples McASP- UART1-RTS GPIO_7 McASP- McASP- McASP- McASP- GPIO_7 GPIO_7 GPIO_7 GPIO_7 ACLKX ACLKX ACLKX ACLKX ACLKX McASP-AFSX SDCARD-IRQ McASP-AFSX McASP-AFSX SDCARD-IRQ GPIO_8...
Page 553: Wake On Pad
Wake-up sources are covered in detail in . 16.8.6 Sense on Power The CC3200 implements a sense on power scheme. By using a few board level pull resistors, the CC3200 can be configured by the user to power up in one of the three following modes: SWRU367D –...
Page 554: Swru367D – June 2014 – Revised May
Table 16-14 shows the pull configurations. I/O Pads and Pin Multiplexing SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 555: Sense-On-Power Configurations
SOP0 and SOP1, on the other hand, are multiplexed with WLAN analog test pins, and not available for application. SWRU367D – June 2014 – Revised May 2018 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 556: A-1. Peripheral Samples
SWRU367D – June 2014 – Revised May 2018 Software Development Kit Examples Software Development Kit Examples The CC3200 SDK kit contains several examples of sample code for most of the peripherals covered in this document. Table A-1 provides links to examples for each of the peripherals. Also refer to the...
Page 557: B-1. Miscellaneous Register Summary
DMA_ICR DMA_ICR Register Section B.1.4 DMA_MIS DMA_MIS Register Section B.1.5 DMA_RIS DMA_RIS Register Section B.1.6 GPTTRIGSEL GPTTRIGSEL Register Section B.1.7 SWRU367D – June 2014 – Revised May 2018 CC3200 Miscellaneous Registers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 558: B-1. Dma_Imr Register
0h = interrupt enabled 1h = disable corresponding interrupt SDIOMWR SDIOM_WR_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt CC3200 Miscellaneous Registers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 559 Table B-2. DMA_IMR Register Field Descriptions (continued) Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt SWRU367D – June 2014 – Revised May 2018 CC3200 Miscellaneous Registers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 560: B-2. Dma_Ims Register
1h = Set mask of the corresponding DMA DONE IRQ SDIOMWR SDIOM_WR_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ CC3200 Miscellaneous Registers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 561 Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ SWRU367D – June 2014 – Revised May 2018 CC3200 Miscellaneous Registers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 562: B-3. Dma_Imc Register
1h = Clear mask of the corresponding DMA DONE IRQ SDIOMWR SDIOM_WR_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ CC3200 Miscellaneous Registers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 563 Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ SWRU367D – June 2014 – Revised May 2018 CC3200 Miscellaneous Registers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 564: B-4. Dma_Icr Register
0h = No effect 1h = Clear corresponding interrupt SDIOMWR SDIOM_WR_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt CC3200 Miscellaneous Registers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 565 Table B-5. DMA_ICR Register Field Descriptions (continued) Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt SWRU367D – June 2014 – Revised May 2018 CC3200 Miscellaneous Registers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 566: B-5. Dma_Mis Register
0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask. 1h = Corresponding interrupt is active and not masked. Read is non- destructive. RESERVED CC3200 Miscellaneous Registers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 567 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask. 1h = Corresponding interrupt is active and not masked. Read is non- destructive. SWRU367D – June 2014 – Revised May 2018 CC3200 Miscellaneous Registers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 568: B-6. Dma_Ris Register
1h = Corresponding interrupt is active. Read is non-destructive. SDIOMWR SDIOM_WR_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive. 1h = Corresponding interrupt is active. Read is non-destructive. CC3200 Miscellaneous Registers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 569 Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive. 1h = Corresponding interrupt is active. Read is non-destructive. SWRU367D – June 2014 – Revised May 2018 CC3200 Miscellaneous Registers Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 570: B-7. Gpttrigsel Register
GT_CCP[7-0]_TRIG_EN External trigger on GT_CCP[7-0] 0h = Disabled 1h = Enabled CC3200 Miscellaneous Registers SWRU367D – June 2014 – Revised May 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
Page 571 Changes from March 31, 2016 to May 30, 2018 (from C Revision (March 2016) to D Revision) ......... Page ..................... • Updated Debug Interface section................• Updated CC3200 Application Processor Interrupts table................. • Updated CPUID Register Field Descriptions table..........• Added DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers section..............
Page 572 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products;...

Texas Instruments CC3200 Technical Reference Manual

Cc3200 Simplelink Wi-Fi and Internet-Of- Things Solution, a Single Chip Wireless Mcu Technical Reference Manual

List of Tables

1 Architecture Overview

2 Cortex-M4 Processor

3 Cortex-M4 Peripherals

4 Direct Memory Access (DMA)

5 General-Purpose Input/Outputs (Gpios)

6 Universal Asynchronous Receivers/Transmitters (Uarts)

7 Inter-Integrated Circuit (I2C) Interface

8 SPI (Serial Peripheral Interface)

9 General-Purpose Timers

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Summary of Contents for Texas Instruments CC3200