Control Pin Interfaces For Soft Pin Mode Or Register Default Mode (Jp18 Hwctrl = Lo) - Texas Instruments LMK03318EVM User Manual

Configuring the EVM
Table 3. Control Pin Interfaces for Soft Pin Mode or Register Default Mode (JP18 HWCTRL = LO)
NAME
COMPONENT
(TYPE)
HWCTRL
JP18
(2-level input)
RSEL
JP17
(3-level input)
GPIO0
JP19
(2-level input)
GPIO1
JP20
(3-level input)
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LMK03318EVM User's Guide
Hardware / Software Control (HW_SW_CTRL) pin
HWCTRL state is sampled on POR and determines the mode of operation.
HWCTRL STATE
LO
(JP Default)
HI
Reference Select (REFSEL) pin for PLL Input Mux
RSEL selects the PLL reference input when external "Pin Select" control is configured by the INSEL_PLL
register bits (R50[1:0] = 01b).
(1)
RSEL STATE
LO
MID
HI
(JP Default)
(1)
RSEL is ignored when INSEL_PLL bits ≠ 01b.
(2)
In Auto Select mode, PRIREF is prioritized over SECREF when a valid signal is detected by the on-
chip reference detector logic. To use the SECREF input in Auto Select mode, the input signal to PRIREF
must be made invalid (disabled or disqualified by the reference detector).
SYNC pin (active low)
GPIO0 can be used to mute the output clocks (when asserted) and trigger output divider synchronization
(when de-asserted) if synchronization is permitted by the SYNC_MUTE and PLL_SYNC_EN register bits.
GPIO0 STATE
LO
HI
(JP Default)
SYNC can also be asserted when switch S4 is pressed.
I2C Slave Address LSB Select pin
GPIO1 is sampled on POR to configure the lower 2 bits of the 7-bit slave address. The upper 5 bits of the
slave address are initialized from EEPROM (SLAVEADR[7:3] = 10100b). By configuring GPIO1, the
composite slave address can be selected as follows:
GPIO1 STATE
LO
(JP Default)
MID
HI
Copyright © 2015, Texas Instruments Incorporated
DESCRIPTION
OPERATING MODE
Soft Pin Mode or Register Default Mode
GPIO[3:2] pins are also sampled on POR to determine the initial
page setting loaded to registers (from EEPROM or default).
Hard Pin Mode
GPIO[5:0] pins are also sampled on POR to determine the initial
page setting loaded to registers (from ROM).
See Table 4: Control Pin Interfaces for Hard Pin Mode (JP18
HWCTRL = HI)
PLL REF INPUT
PRIREF
SECREF
Auto Select
SYNC OPERATION
Assert SYNC: Outputs muted, dividers in reset
Normal output operation
7-BIT SLAVE ADDRESS
(excludes W/R bit)
1010000b / 0x50
1010001b / 0x51
1010011b / 0x53
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(2)
SNAU186 – November 2015
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