Table 3-2. Adcctl2 Register - Texas Instruments TMS320F28004 Series Manual

Real-time mcus silicon errata silicon revisions b, a, 0

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Silicon Revision B Usage Notes and Advisories

Advisory

ADC: Degraded ADC Performance With ADCCLK Fractional Divider

Revisions Affected 0, A, B

Details

Using fractional SYSCLK-to-ADCCLK dividers (controlled by the ADCCTL2.PRESCALE

field) has been shown to cause degradation in ADC performance on this device. See

Table

Workaround

Use even PRESCALE clock divider values. Even PRESCALE values result in integer

clock dividers which do not impact the ADC performance.

Advisory

ADC: DMA Read of Stale Result

Revisions Affected 0, A, B

Details

The ADCINT flag can be set before the ADCRESULT value is latched (see the t

and t

Microcontrollers

3 cycles after the ADCINT trigger is set. As a result, the DMA could read a prior

ADCRESULT value when the user expects the latest result if all of the following are true:

•

Only the DMA reads listed above could result in reads of stale data; the following non-

DMA methods will always read the expected data:

•

Workaround

Trigger two DMA channels from the ADCINT flag. The first channel acts as a dummy

transaction. This will result in enough delay that the second channel will always read the

fresh ADC result.

TMS320F28004x Real-Time MCUs Silicon Errata

Silicon Revisions B, A, 0

3-2.

BIT

FIELD

3–0

PRESCALE

BIT

FIELD

3–0

PRESCALE

columns in the ADC Timings table of the

INT(LATE)

data sheet). The DMA can read the ADCRESULT value as soon as

The ADC is in late interrupt mode.

The ADC operates in a mode where t

(ADCCTL2 [PRESCALE] > 2).

The DMA is triggered from the ADCINT signal.

The DMA immediately reads the ADCRESULT value associated with that ADCINT

signal without reading any other values first.

The DMA was idle when it received the ADCINT trigger.

The ADCINT flag triggers a CLA task.

The ADCINT flag triggers a CPU ISR.

The CPU polls the ADCINT flag.