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25.6.7 Configuration and Control (CFGCTRL) Register, offset 0xD14
The Configuration and Control (CFGCTRL) register controls entry to Thread mode and enables: the
handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults;
trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged
software.
Note: This register can only be accessed from privileged mode.
31
10
9
Rsvd
STKALIGN
BFHFNMIGN
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-45. Configuration and Control (CFGCTRL) Register Field Descriptions
Bit
Field
31-10
Reserved
9
STKALIGN
8
BFHFNMIGN
7-5
Reserved
4
DIV0
3
UNALIGNED
2
Reserved
1
MAINPEND
0
BASETHR
SPRUH22I – April 2012 – Revised November 2019
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Figure 25-38. Configuration and Control (CFGCTRL) Register
8
7
5
Reserved
R/W-0
R-0
R/W-0
Value
Description
Reserved
Stack Alignment on Exception Entry
0
The stack is 4-byte aligned.
1
The stack is 8-byte aligned.
On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On
return from the exception, it uses this stacked bit to restore the correct stack alignment.
Ignore Bus Fault in NMI and Fault.
This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store
instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated
handlers.
0
Data bus faults caused by load and store instructions cause a lock-up. 0
1
Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit only when the handler and its data are in absolutely safe memory. The normal use of
this bit is to probe system devices and bridges to detect control path problems and fix them.
Reserved
Trap on Divide by 0. This bit enables faulting or halting when the processor executes an SDIV or
UDIV instruction with a divisor of 0.
0
Do not trap on divide by 0. A divide by zero returns a quotient of 0.
1
Trap on divide by 0.
Trap on Unaligned Access
0
Do not trap on unaligned halfword and word accesses.
1
Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether
UNALIGNED is set.
Reserved
Allow Main Interrupt Trigger
0
Disables unprivileged software access to the SWTRIG register.
1
Enables unprivileged software access to the SWTRIG register.
Thread State Control
0
The processor can enter Thread mode only when no exception is active.
1
The processor can enter Thread mode from any level under the control of an EXC_RETURN value
(see the Cortex-M3 Processor chapter for more information).
Copyright © 2012–2019, Texas Instruments Incorporated
System Control Block (SCB) Register Descriptions
Reserved
R-0
4
3
DIV0
UNALIGNED
Reserved
R/W-0
2
1
MAINPEND
R-0
R/W-0
Cortex-M3 Peripherals
16
0
BASETHR
R/W-0
1637
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