Cfgctrl Register; Cfgctrl Register Field Descriptions - Texas Instruments SimpleLink MSP432E4 Technical Reference Manual

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SCB Registers

2.5.7 CFGCTRL Register (Offset = 0xD14) [reset = 0x200]

Configuration and Control (CFGCTRL)

NOTE: This register can only be accessed from privileged mode.

The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and

faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned

accesses; and access to the SWTRIG register by unprivileged software (see ).

CFGCTRL is shown in

Cortex-M4 Peripherals

and described in

Figure 2-19. CFGCTRL Register

Table 2-32. CFGCTRL Register Field Descriptions

Stack Alignment on Exception Entry

On exception entry, the processor uses bit 9 of the stacked PSR to

indicate the stack alignment. On return from the exception, it uses

this stacked bit to restore the correct stack alignment.

Ignore Bus Fault in NMI and Fault

This bit enables handlers with priority -1 or -2 to ignore data bus

faults caused by load and store instructions. The setting of this bit

applies to the hard fault, NMI, and FAULTMASK escalated handlers.

Set this bit only when the handler and its data are in absolutely safe

memory. The normal use of this bit is to probe system devices and

bridges to detect control path problems and fix them.

Trap on Divide by 0

This bit enables faulting or halting when the processor executes an

SDIV or UDIV instruction with a divisor of 0.

Trap on Unaligned Access

Unaligned LDM, STM, LDRD, and STRD instructions always fault

regardless of whether UNALIGNED is set.

Allow Main Interrupt Trigger

Thread State Control

SLAU723A – October 2017 – Revised October 2018

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