Register 60: Configuration And Control (Cfgctrl), Offset 0Xd14 - Texas Instruments TM4C1294NCPDT Datasheet

Register 60: Configuration and Control (CFGCTRL), offset 0xD14

Note: This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 163).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type RW, reset 0x0000.0200
31 30 29
Type RO RO RO
Reset 0 0 0
15 14 13
reserved
Type RO RO RO
Reset 0 0 0
Bit/Field Name
31:10 reserved
9 STKALIGN
8 BFHFNMIGN
7:5 reserved
June 18, 2014
28 27 26 25
RO RO RO RO
0 0 0 0
12 11 10 9
STKALIGN
RO RO RO RW
0 0 0 1
Type Reset
RO 0x0000.00
RW 1
RW 0
RO 0x0
Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller
24 23 22 21
reserved
RO RO RO RO
0 0 0 0
8 7 6 5
reserved
BFHFNMIGN
RW RO RO RO
0 0 0 0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stack Alignment on Exception Entry
Value Description
0 The stack is 4-byte aligned.
1 The stack is 8-byte aligned.
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Value Description
0 Data bus faults caused by load and store instructions cause a
lock-up.
1 Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20 19 18 17
RO RO RO RO
0 0 0 0
4 3 2 1
DIV0 reserved
UNALIGNED MAINPEND
RW RW RO RW
0 0 0 0
16
RO
0
0
BASETHR
RW
0
175