Register Description - Texas Instruments CC3200 Technical Reference Manual

Register Description

4.3 Register Description
4.3.1 DMA Register Map
Table 4-4 lists the μDMA channel control structures and registers. The channel control structure shows the
layout of one entry in the channel control table. The channel control table is located in system memory,
and the location is determined by the application; thus, the base address is n/a (not applicable) and noted
as so above the register descriptions. In
offset from the entry in the channel control table. See
channel control table are located in memory. The μDMA register addresses are given as a hexadecimal
increment, relative to the μDMA base address of 0x400F.F000. Note that the μDMA module clock must be
enabled before the registers can be programmed. There must be a delay of three system clocks after the
μDMA module clock is enabled before any μDMA module registers are accessed.
Offset
0x000
0x004
0x008
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x04C
108
Direct Memory Access (DMA)
Table
Table 4-4. µDMA Register Map
Name
μDMA Channel Control Structure (Offset from Channel Control Table Base)
DMA_SRCENDP
DMA_DSTENDP
DMA_CHCTL
μDMA Registers (Offset from μDMA Base Address)
DMA_STAT
DMA_CFG
DMA_CTLBASE
DMA_ALTBASE
DMA_WAITSTAT
DMA_SWREQ
DMA_USEBURSTSET
DMA_USEBURSTCLR
DMA_REQMASKSET
DMA_REQMASKCLR
DMA_ENASET
DMA_ENACLR
DMA_ALTSET
DMA_ALTCLR
DMA_PRIOSET
DMA_PRIOCLR
DMA_ERRCLR
Copyright © 2014–2018, Texas Instruments Incorporated
4-4, the offset for the channel control structures is the
Table 4-1 for a description of how the entries in the
Type Reset
R/W
R/W
R/W
RO 0x001F.0000
WO
R 0x0000.0000
RO 0x0000.0200
RO 0x03C3.CF00
WO
R/W 0x0000.0000
WO
R/W 0x0000.0000
WO
R/W 0x0000.0000
WO
R/W 0x0000.0000
WO
R/W 0x0000.0000
WO
R/W 0x0000.0000
SWRU367D – June 2014 – Revised May 2018
www.ti.com
Description
- DMA Channel Source
Address End Pointer
- DMA Channel
Destination Address End
Pointer
- DMA Channel Control
Word
- DMA Configuration
DMA Channel Control
Base Pointer
DMA Alternate Channel
Control Base
Pointer
DMA Channel Wait-on-
Request Status
- DMA Channel Software
Request
DMA Channel Useburst
Set
- DMA Channel Useburst
Clear
DMA Channel Request
Mask Set
- DMA Channel Request
Mask Clear
DMA Channel Enable
Set
- DMA Channel Enable
Clear
DMA Channel Primary
Alternate Set
- DMA Channel Primary
Alternate Clear
DMA Channel Priority
Set
- DMA Channel Priority
Clear
DMA Bus Error Clear
Submit Documentation Feedback