Advisory - Fpu: Fpu-To-Cpu Register Move Operation Preceded By Any Fpu 2P Operation - Texas Instruments Silicon Errata TMS320F28379S Instruction Manual

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Advisory
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation
B, C
Revision(s) Affected
This advisory applies when a multi-cycle (2p) FPU instruction is followed by a FPU-to-
Details
CPU register transfer. If the FPU-to-CPU read instruction source register is the same as
the 2p instruction destination, then the read may be of the value of the FPU register
before the 2p instruction completes. This occurs because the 2p instructions rely on
data-forwarding of the result during the E2 phase of the pipeline. If a pipeline stall
happens to occur in the E3 phase, the result does not get forwarded in time for the read
instruction.
The 2p instructions impacted by this advisory are MPYF32, ADDF32, SUBF32, and
MACF32. The destination of the FPU register read must be a CPU register (ACC, P, XT,
XAR0...XAR7). This advisory does not apply if the register read is a FPU-to-FPU
register transfer.
In the example below, the 2p instruction, MPYF32, uses R6H as its destination. The
FPU register read, MOV32, uses the same register, R6H, as its source, and a CPU
register as the destination. If a stall occurs in the E3 pipeline phase, then MOV32 will
read the value of R6H before the MPYF32 instruction completes.
Example of Problem:
|| MOV32 *XAR7++, R4H
|| MOV32 *--SP, R2H
Treat MPYF32, ADDF32, SUBF32, and MACF32 in this scenario as 3p-cycle
Workaround(s)
instructions. Three NOPs or non-conflicting instructions must be placed in the delay slot
of the instruction.
The C28x code generation tools v.6.2.0 and later will both generate the correct
instruction sequence and detect the error in assembly code. In previous versions, v6.0.5
(for the 6.0.x branch) and v.6.1.2 (for the 6.1.x branch), the compiler will generate the
correct instruction sequence but the assembler will not detect the error in assembly
code.
Example of Workaround:
SPRZ422D – August 2014 – Revised July 2016
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Usage Notes and Known Design Exceptions to Functional Specifications
MPYF32 R6H, R5H, R0H
F32TOUI16R R3H, R4H
ADDF32 R2H, R2H, R0H
MOV32 @XAR3, R6H
MPYF32 R6H, R5H, R0H
|| MOV32 *XAR7++, R4H
F32TOUI16R R3H, R4H
ADDF32 R2H, R2H, R0H
|| MOV32 *--SP, R2H
NOP
MOV32 @XAR3, R6H
Copyright © 2014–2016, Texas Instruments Incorporated
; 2p FPU instruction that writes to R6H
; delay slot
; alignment cycle
; FPU register read of R6H
; 3p FPU instruction that writes to R6H
; delay slot
; delay slot
; alignment cycle
; FPU register read of R6H
TMS320F2837xS Delfino™ Microcontrollers
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