Wdtris Register - Texas Instruments CC3200 Technical Reference Manual

Register Map
10.3.1.1.5 WDTRIS Register (offset = 10h) [reset = 0h]
WDTRIS is shown in
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this
register if the controller interrupt is masked.
31 30
23 22
15 14
7 6
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit Field
31-1 RESERVED
0 WDTRIS
336
Watchdog Timer
Figure 10-6 and described in
Figure 10-6. WDTRIS Register
29 28
RESERVED
21 20
RESERVED
13 12
RESERVED
5 4
RESERVED
R-0h
Table 10-7. WDTRIS Register Field Descriptions
Type Reset
R 0h
R 0h
Copyright © 2014–2018, Texas Instruments Incorporated
Table 10-7.
27 26
R-0h
19 18
R-0h
11 10
R-0h
3 2
Description
Watchdog Raw Interrupt Status
0h = The watchdog has not timed out.
1h = A watchdog time-out event has occurred.
SWRU367D – June 2014 – Revised May 2018
www.ti.com
25 24
17 16
9 8
1 0
WDTRIS
R-0h
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