Sony BVW-55 Maintenance Manual page 608

IC
CXD8953Q (SONY)
C-MOS ERROR DETECTION AND HANDLING
—TOP VIEW—
81
85
V
DD
90
GND
95
100
PIN PIN
I/O SIGNAL I/O SIGNAL
No. No.
1 O TEST0 21 I IDATA8
2 — V 22 I IDATA9
DD
3 — V 23 I FORM0
DD
4 O TEST1 24 I FORM1
5 O TEST2 25 I AUTO
6 I TEST3 26 I MODE0
7 I TEST4 27 I MODE1
8 O TEST5 28 I MODE2
9 I ICLOCK 29 O OTHANC
10 I IDATA0 30 O EDHVLD
11 I IDATA1 31 O DPR
12 I IDATA2 32 O INTR
13 I IDATA3 33 I/O D7
14 — GND 34 I/O D6
15 — GND 35 I/O D5
16 — GND 36 I/O D4
17 I IDATA4 37 I/O D3
18 I IDATA5 38 I/O D2
19 I IDATA6 39 I/O D1
20 I IDATA7 40 I/O D0
10 - 3,
17 - 22
IDATA0 -
IDATA9
FORMAT
31
DPR
23
FORM0
24
FORM1
25
AUTO
77
OD1
78
OL525
29
OTHANC
27
MODE1
28
MODE2
51
RESET
59
OCLOCK
9
ICLOCK
6, 7, 41,
TEST3, TEST4,
50, 79, 80
TEST6, TEST8,
TEST14, TEST15
1, 4, 5, 8, 49,
TEST0 - TEST2,
54-56, 58, 76
TEST5, TEST7,
TEST9 - TEST13
2-58
50
45
40
35
31
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
No. No. No.
41 I TEST6 61 O ODATA8 81
42 I A3 62 O ODATA7 82
43 I A2 63 — V 83
DD
44 I A1 64 O ODATA6 84
45 I A0 65 — GND 85
WRITE
46 I 66 — GND 86
READ
47 I 67 — GND 87
CS
48 I 68 O ODATA5 88
49 O TEST7 69 O ODATA4 89
50 I TEST8 70 O ODATA3 90
RESET
51 I 71 O ODATA2 91
52 — V 72 — V 92
DD DD
53 — V 73 O ODATA1 93
DD
54 O TEST9 74 — GND 94
55 O 75 O 95
TEST10 ODATA0
56 O TEST11 76 O TEST13 96
57 — GND 77 O OD1 97
58 O TEST12 78 O OL525 98
59 O OCLOCK 79 I TEST14 99
60 O ODATA9 80 I TEST15 100
ANC CHECK
LATCH DELAY
PARITY
CHECK
VIDEO0 - 9
ENABLE
TIMING
EAV TRS
TIMING
DETECT GEN
INTRRUPT PULSE
DATA
DETECT
FORMAT
SELECT
525/625 422/4FC
DATA
DETECT
FLAG
DATA
DETECT
INPUT
A0 - A3
AUTO
CS
FORM0, FORM1
ICLOCK
IDATA0 - IDATA9
MODE0
MODE1
MODE2
READ
RESET
TEST3, TEST4, TEST6,
TEST8, TEST14, TEST15
WRITE
OUTPUT
I/O SIGNAL
ANCER
O APERR
APERR
O FFERR
DPR
O ANCER
EDHVLB
I/O ANCEDH
FFERR
I/O ANCEDA
INTR
I/O ANCIDH
OCLOCK
I/O ANCIDA
OD1
— V
DD
ODATA0 - ODATA9
I/O ANCUES
OL525
I/O APEDH
OTHANC
I/O APEDA
TEST0 - TEST2, TEST5,
— GND
TEST7, TEST9 - TEST13
I/O APIDH
I/O APIDA
I/O APUES
INPUT/OUTPUT
I/O FFEDH
ANCEDA
I/O FFEDA
ANCEDH
I/O FFIDH
ANCIDA
I/O FFIDA
ANCIDH
I/O FFUES
ANCUES
APEDA
APEDH
APIDA
APIDH
APUES
D0 - D7
FFEDA
FFEDH
FFIDA
FFIDH
FFUES
DELAY
EDH DATA GENERATOR
SUM
ANC & EDH HEADER
ANCILLARY ERROR
&
3FF
000
HEADER
DID
BNO
DC
AP
AP CRC DATA
CRC
GEN
EDH DATA
ADD TIMING
AP
ERROR
CRC
DETECT
FF CRC DATA
FF
CRC
GEN
ERROR
DETECT
FF
CRC
FLAG
DATA
ERROR
FLAG
SELECTOR
FLAG DATA
FLAG DATA
CONVERTER
(EDH → EDA)
FLAG DATA from CPU
(EDH IDH UES)
FLAG DATA from EXT
FLAG DATA to CPU
FLAG DATA to EXT
: ADDRESS
: AUTO DETECT
: CHIP SELECT
: VIDEO FORMAT
: CLOCK
: VIDEO DATA
: 1 = Detect each FLAG and calculate CRC.
Add the result and output.
0 = Input each FLAG from outside and calculate CRC.
Add the result and output.
: 1 = If other ANCILLARY DATA existe EDH,
such as AUDIO, no EDH is added.
0 = EDH is added unconditionally.
: MODE SELECT
: READ
: RESET
: TEST
: WRITE
: ANCILLARY DATA ERROR
: ACTIVE PICTURE ERROR
: INPUT SIGNAL DETECT
: ERROR DETECTION & HANDLING CORRESPOND DETECT
: FULL FIELD ERROR
: INTERRUPT
: OUTPUT CLOCK
: D1/D2 FORMAT SELECT
: OUTPUT DATA
: 525/625, 422/4FC FORMAT SELECT
: OTHER ANC DATA DETECT
: TEST
: ANCILLARY EDA FLAG
: ANCILLARY EDH FLAG
: ANCILLARY IDA FLAG
: ANCILLARY IDH FLAG
: ANCILLARY UES FLAG
: ACTIVE PICTURE EDA FLAG
: ACTIVE PICTURE EDH FLAG
: ACTIVE PICTURE IDA FLAG
: ACTIVE PICTURE IDH FLAG
: ACTIVE PICTURE UES FLAG
: CPU DATA
: FULL FIELD EDA FLAG
: FULL FIELD EDH FLAG
: FULL FIELD IDA FLAG
: FULL FIELD IDH FLAG
: FULL FIELD UES FLAG
75, 73,
71 - 68, 64,
63 - 60
EDH
DATA
INSERT
CHECK
MIX
SUM
GEN
83
AP ERROR
81
FF ERROR 82
INTERRUPT
32
MODE
CONT
INTERRUPT
MODE
40 - 33
45 - 42
WRITE
46
DATA
48
CRC DATA
READ
DATA
ERROR
SELECT
47
26
84 - 87,
89 - 91,
93 - 100
ODATA0 -
ODATA9
ANCER
APERR
FFERR
INTR
D0-D7
A0-A3
WRITE
CS
READ
MODE0
ANCEDA, ANCEDH,
ANCIDA, ANCIDH,
ANCUES, APEDA,
APEDH, APIDA,
APIDH, APUES,
FFEDA, FFEDH,
FFIDA, FFIDH,
FFUES
BVW-55