Sony BVW-55 Maintenance Manual page 638

IC
UPD485506G5-25-7JF-E2 (NEC)
C-MOS 80 K-BIT FIFO MEMORY
—TOP VIEW—
DO0 1 44 DI0
DO1 2 43 DI1
DO2 3 42 DI2
DO3 4 41 DI3
DO4 5 40 DI4
DO5 6 39 DI5
DO6 7 38 DI6
DO7 8 37 DI7
OE WE
9 36
RE
10 35 MD
11 GND GND 34
RSTR RSTW
12 33
RCK 13 32 WCK
14 V V 31
DD DD
DO8 15 30 DI8
DO9 16 29 DI9
DO10 17 28 DI10
DO11 18 27 DI11
DO12 19 26 DI12
DO13 20 25 DI13
DO14 21 24 DI14
DO15 22 23 DI15
33
RSTW
WRITE ADDRESS POINTER
32
WCK
36
WE
44
DI0
43
DI1
42
DI2
41
DI3
40
DI4
39
DI5
38
DI6
37
DI7
30
DI8
29
DI9
28
DI10
27
DI11
26
DI12
25
DI13
24
DI14
23
DI15
2-88
1
44
DI0 DO0
43 2
DI1 DO1
42 3
DI2 DO2
41 4
DI3 DO3
40 5
DI4 DO4
39 6
DO5
DI5
38 7
DI6 DO6
8
37
DI7 DO7
30 15
DI8 DO8
29 16
DI9 DO9
28 17
DI10 DO10
27 18
DI11 DO11
26 19
DI12 DO12
25 20
DI13 DO13
24 21
DI14 DO14
23 22
DI15 DO15
10
RE
36
WE
12
RSTR
33
RSTW
13
RCK
32
WCK
35
MD
OE
9
INPUT
DI0 - DI15 : DATA
MD : MODE SETTING
OE
: OUTPUT ENABLE
RCK : READ CLOCK
RE
: READ ENABLE
RSTR
: RESET READ
RSTW
: RESET WRITE
WCK : WRITE CLOCK
WE
: WRITE ENABLE
OUTPUT
DO0 - DO15 : DATA
READ ADDRESS POINTER
40,384 BITS
( 5,048 BY 8)
MEMORY CELL ARRAY
40,384 BITS
( 5,048 BY 8)
MEMORY CELL ARRAY
MODE CONTROLLER
35
MD
UPD71055GB-10-3B4 (NEC)
C-MOS PARALLEL INTERFACE UNIT
—TOP VIEW—
44 43 42 41 40 39 38 37 36 35 34
INDEX
NC
1
CS
2
3
4 GND
A1
5
A0
6
P27
7
P26
8
P25
9
P24
10
P20
11
P21
12 13 14 15 16 17 18 19 20 21 22
A1, A0 ; ADDRESS
CS
; CHIP SELECT
D7 - D0 ; DATA BUS
P07 - P00 ; PORT 0
IC ; INTERNALLY CONNECTED
CS RD WR A1 A0
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 0 0 X X
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
DATA • BUS → COMMAND REGISTER
0 1 0 1 1
0 1 1 X X
1 X X X X
V
DD
24 - 31
DATA BUS
GND D7 - D0
BUFF
12
RSTR
13
RCK
10
RE
1
DO0
2
DO1
3
44
DO2
RD
4
35
DO3
WR
READ/
5
4
DO4
WRITE
A1
6
5
DO5 CONTROL
A0
7
32
DO6
RESET
8
DO7
2
CS
9
OE
15
DO8
16
DO9
17
DO10
18
DO11
19
DO12
20
DO13
21
DO14
22
DO15
X24164SIT1 (XICOR)(16K BIT)
C-MOS SERIAL EEPROM
—TOP VIEW—
S0 1 V 8
IN DD
S1
2 7
IN
S2 3 6
IN
4 GND 5
NC
NC
33
RESET
32
31
D0
30 D1
29
D2
28 D3
27 D4
26 D5
25 D6
D7
24
V 23
DD
P17 - P10 ; PORT 1
P27 - P20 ; PORT 2
RD
; READ STROBE
WR
; WRITE STROBE
OPERATION CPU ACTION
PORT0 → DATA • BUS
INPUT
PORT1 → DATA • BUS
INPUT
PORT2 → DATA • BUS
INPUT
DISABLE
DATA • BUS → PORT0
OUTPUT
DATA • BUS → PORT1
OUTPUT
DATA • BUS → PORT2
OUTPUT
OUTPUT
HIGH IMPEDANCE
8
8
36 - 43
PORT 0
GROUP
CONTROL
6 - 9
8
PORT 2
13 - 10
COMMAND
REGISTER
22 - 18,
16 - 14
8
PORT 1
GROUP
CONTROL
INPUT
S1
S0, , S2 : DEVICE SELECT
SCL : SERIAL CLOCK
WP : WRITE PROTECT
WP
IN
INPUT/OUTPUT
SCL
IN
SDA : SERIAL DATA
SDA
I/O
43
P00
42
P01
41
P02
2 40
P03
CS
39
P04
5 38
P05
A0
4 37
A1 P06
36
P07
35 14
P10
WR
44 15
RD P11
16
P12
24 18
D7 P13
25 19
D6 P14
26 20
D5 P15
27 21
D4 P16
28 22
D3 P17
29 10
D2 P20
30 11
D1 P21
31 12
D0 P22
13
P23
32 9
RESET P24
8
P25
7
P26
6
P27
0 : LOW LEVEL
1 : HIGH LEVEL
X : DON'T CARE
P07 - P00
P27 - P24
P23 - P20
P17 - P10
BVW-55