Simultaneous Multithreading - IBM z13s Technical Manual

Performance per watt improvements when compared to the zBC12 system
Enhanced instruction dispatch and grouping efficiency
Enhanced branch prediction structure and sequential instruction fetching
Millicode improvements
Decimal floating-point (DFP) improvements
The z13s enhanced Instruction Set Architecture (ISA) includes a set of instructions that are
added to improve compiled code efficiency. These instructions optimize PUs to meet the
demands of a wide variety of business and analytics workload types without compromising
the performance characteristics of traditional workloads.

3.4.1 Simultaneous multithreading

z13s servers, aligned with industry directions, can process up to two simultaneous threads in
a single core while sharing certain resources of the processor, such as execution units,
translation lookaside buffers (TLBs), and caches. When one thread in the core is waiting for
other hardware resources, the second thread in the core can use the shared resources rather
than remaining idle. This capability is known as SMT.
SMT is only supported by Integrated Facility for Linux (IFL) and IBM z Systems Integrated
Information Processor (zIIP) speciality engines on z13s servers, and it requires operating
system support. An operating system with SMT support can be configured to dispatch work to
a thread on a zIIP (for eligible workloads in z/OS) or an IFL (for z/VM) core in single thread or
SMT mode so that HiperDispatch cache optimization can be considered. For more
information about operating system support, see Chapter 7, "Software support" on page 229.
To support SMT, z13s servers have a double symmetric instruction pipeline width and full
architectural state per thread. Beyond this, the CPU address changes and the 16-bit CPU ID
consist of 15-bit core ID and a 1-bit thread ID. For example, the CPU ID 6
(b'0000000000000110') means core 3 thread 0 and the CPU ID 7(b'0000000000000111')
means core 3 thread 1. For CPs, only thread 0 is used in each core.
SMT technology allows instructions from more than one thread to run in any pipeline stage at
a time. Each thread has its own unique state information, such as PSW and registers. The
simultaneous threads cannot necessarily run instructions instantly and must at times
compete to use certain core resources that are shared between the threads. In some cases,
threads can use shared resources that are not experiencing competition.
Chapter 3. Central processor complex system design
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